David Harris
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1326ade1a0
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Removed depricated N-mode support and SI/EDELEG registers. rv64gc_wally64priv tests are failing, but seem to be failing before this change.
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2022-02-15 19:20:41 +00:00 |
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David Harris
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38bbe23d14
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More config file cleanup; 32ic tests broken
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2022-02-03 01:08:34 +00:00 |
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David Harris
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02071700d6
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Removed Busybear dependencies
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2022-02-02 20:28:21 +00:00 |
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Ross Thompson
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c2b2fae98d
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-01-31 12:17:37 -06:00 |
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David Harris
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090533cfe9
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Replaced || and && with | and &
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2022-01-31 01:07:35 +00:00 |
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Ross Thompson
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06209c417f
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Cleaned up the InstrMisalignedFault.
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2022-01-28 13:19:24 -06:00 |
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Ross Thompson
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862bf2faae
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Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
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2022-01-27 17:11:27 -06:00 |
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Ross Thompson
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e2343699d1
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Factored out InstrValidNotFlushedM from each csr*.sv to csr.sv
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2022-01-20 16:39:54 -06:00 |
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Ross Thompson
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4a75e69457
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Merged in the debug ila updates.
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2022-01-18 17:29:21 -06:00 |
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Ross Thompson
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a5f773220e
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Updated CSR modules to prevent writting the registers when flushing. This only effects architecture writes not side effect writes.
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2022-01-18 17:19:33 -06:00 |
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Ross Thompson
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e06fb923a1
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Better solution to the integer divider interrupt interaction.
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2022-01-12 14:22:18 -06:00 |
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Ross Thompson
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b294f1fbb0
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Oups. My hack for DivE interrupt prevention was wrong.
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2022-01-12 14:17:16 -06:00 |
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Ross Thompson
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459f4bd3b4
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Hack "fix" to prevent interrupt from occuring during an integer divide.
This is not the desired solution but will allow continued debuging of linux.
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2022-01-12 14:17:16 -06:00 |
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Ross Thompson
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73c488914f
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Added icache access and icache miss to performance counters.
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2022-01-09 22:56:56 -06:00 |
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David Harris
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120fb7863f
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Reformatted MIT license to 95 characters
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2022-01-07 12:58:40 +00:00 |
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David Harris
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c1d6550ccb
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Removed generate statements
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2022-01-05 14:35:25 +00:00 |
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David Harris
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b36ace221e
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Renamed wally-pipelined to pipelined
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2022-01-04 19:47:41 +00:00 |
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