58 Commits

Author	SHA1	Message	Date
Ross Thompson	3bec276862	Added tim only test to regression-wally. Minor cleanup to ifu.	2022-01-14 11:13:06 -06:00
Ross Thompson	a973681a90	Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.	2022-01-13 22:21:43 -06:00
Ross Thompson	aad28366d7	Partial local dtim in lsu configuration.	2022-01-13 17:50:31 -06:00
Ross Thompson	960af4b70f	Set rv32ic to not use icache.	2022-01-12 14:10:09 -06:00
David Harris	401a5b1779	Removed unused coremark_bare	2022-01-10 05:05:55 +00:00
David Harris	39d5570d2c	Added riscvsingle. Removed unnecessary coremark config. Added compiler flags for Coremark.	2022-01-10 05:04:13 +00:00
Ross Thompson	06168e67e4	Switched block for line in caches.	2022-01-04 22:08:18 -06:00
David Harris	b36ace221e	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00