David Harris
1166c40059
FPU generates illegal instruction if MSTATUS.FS = 00
2022-05-03 11:56:31 +00:00
Kip Macsai-Goren
bd87af478a
Changed mtval for instruction misaligned fault to get address from ieuAdrM (Jal/branch target address)
2022-04-22 22:46:11 +00:00
Ross Thompson
2376d66ec2
Added more ILA signals.
2022-04-02 16:39:45 -05:00
bbracker
69a0f6e00b
big interrupts refactor
2022-03-30 13:22:41 -07:00
bbracker
8ea25e591b
fix typo that Madeleine found
2022-03-28 15:39:29 -07:00
bbracker
d33de3ef6b
tabs vs spaces disagreement
2022-03-24 17:11:41 -07:00
bbracker
4b376e2834
1st attempt at multiple channel PLIC
2022-03-24 17:08:10 -07:00
Ross Thompson
71aad2d213
Moved WriteDataM register into LSU.
2022-03-23 14:17:59 -05:00
Ross Thompson
654c4d1148
simplified uncore's name for HWDATA.
2022-03-10 18:17:44 -06:00
Ross Thompson
565ca4e4a3
Broken state. address translation not working after changes to hptw to support atomic updates to PT.
2022-02-16 23:37:36 -06:00
Ross Thompson
862bf2faae
Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
2022-01-27 17:11:27 -06:00
David Harris
07425369fc
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
David Harris
fd13272d4c
Renamed LSUStall to LSUStallM
2022-01-15 00:24:16 +00:00
Ross Thompson
e06fb923a1
Better solution to the integer divider interrupt interaction.
2022-01-12 14:22:18 -06:00
Ross Thompson
459f4bd3b4
Hack "fix" to prevent interrupt from occuring during an integer divide.
...
This is not the desired solution but will allow continued debuging of linux.
2022-01-12 14:17:16 -06:00
Ross Thompson
73c488914f
Added icache access and icache miss to performance counters.
2022-01-09 22:56:56 -06:00
Ross Thompson
509a0cd3f8
Fixed bug with interlock fsm. The interlock fsm should suppress bus and cache requests by the cpu
...
only at the start of a request. Pending interrupt was used to start one of these suppressions;
however because of the way the cache's fsm was separated from the bus fsm, the cache now made requests
to the bus fsm. On a miss with write back, the inital fetch is handled correctly. However if an
interrupt becam pending then the the next request (eviction) made by the cache was also suppressed.
This keeps the d cache fsm stuck in the STATE_MISS_EVICT_DIRTY state as it think it has made a request
to the bus fsm, but the pending interrupt ignored the request.
The solution is to modify how cpu requests are suppressed. Instead of relying on pending interrupt
it is better to use interrupt which will be disabled if the dcache is currently processing the evict.
2022-01-07 17:55:34 -06:00
David Harris
120fb7863f
Reformatted MIT license to 95 characters
2022-01-07 12:58:40 +00:00
David Harris
2a64b1bc95
Used .* in wrapper
2022-01-07 05:23:42 +00:00
David Harris
1d8451c2cf
Capitalized LSU and IFU, changed MulDiv to MDU
2022-01-07 04:30:00 +00:00
David Harris
e5f9fbb238
Fixed multiplier nan boxing bug
2022-01-06 23:03:29 +00:00
David Harris
85fa620cfb
Finished removing generate statements
2022-01-05 16:41:17 +00:00
David Harris
b36ace221e
Renamed wally-pipelined to pipelined
2022-01-04 19:47:41 +00:00
