Ross Thompson
c9c4f63c18
Fixed remaining bugs in the imperas merge.
2023-01-31 13:04:26 -06:00
Ross Thompson
026071e247
Merge branch 'imperas'
2023-01-31 12:46:22 -06:00
Ross Thompson
cc48cdc97b
Imperas found a real bug in virtual memory.
...
If the instruction address spilled across two pages and the second page misses the TLB,
the HPTW received a tlb miss at the address of the first page rather than the second.
After the walk the TLB was updated with the PTE from the first page at the address of the
second page.
Example bug
Instruction PCF = 0x2ffe
First page in 0x2ffe and second page in 0x3000.
The second page misses the TLB and generates HPTW request at 0x2ffe rather than 0x3000.
TLB is updated with PTE from 0x2ffe at 0x3000.
2023-01-30 11:47:51 -06:00
eroom1966
7c0cad148d
Partial fix for misaligned LD/ST
2023-01-18 17:11:39 +00:00
eroom1966
2e4e5f9c61
changes made with Ross
2023-01-18 16:46:48 +00:00
Ross Thompson
b30c13a188
Fixed the rvvi CSR write enable not synchronized with a valid instruction in the Writeback stage.
2023-01-17 18:24:46 -06:00
Ross Thompson
caff6e788c
Somehow the imperas files spilled into the main branch.
2023-01-17 15:39:34 -06:00
eroom1966
f4e7e54abe
Code refactor and addition of rvvi interface
2023-01-17 12:47:38 +00:00
Ross Thompson
fabe13bdce
Fixed issue with rvvi tracer so it reports call csr changes, not just instrutions which write the CSRs.
2023-01-16 13:35:06 -06:00
Ross Thompson
395b7a5b32
Nearly complete RVVI tracer.
...
Missing PMP registers and performance counters other than MCYCLE and MINSTRET.
2023-01-12 18:43:39 -06:00
Ross Thompson
ef4c684336
Added supervisor mode registers to tracer.
2023-01-12 17:04:41 -06:00
Ross Thompson
9917be817c
Added M CSRs to the CSRArray.
2023-01-12 16:51:51 -06:00
Ross Thompson
a68773eba1
added machine csr to logger.
2023-01-12 16:35:19 -06:00
Ross Thompson
2e622c9860
Added support to print the gprs.
2023-01-12 16:09:30 -06:00
Ross Thompson
4733b787f8
rvvi trace is coming alone nicely.
2023-01-12 14:46:31 -06:00
David Harris
c3bca40e05
Added WFI to the testbench instruction name decoder
2022-04-14 17:12:11 +00:00
David Harris
f734afb866
Just needed to recompile - all good. Now removed uretM because N-mode is depricated
2022-02-15 19:48:49 +00:00
Ross Thompson
143bdaa288
Modified makefiles to generate function address to name mappings for modelsim.
2022-02-01 18:25:03 -06:00
Ross Thompson
f055441ecf
Improved function_radix to not printout warnings when no valid function is found.
2022-02-01 18:03:09 -06:00
David Harris
07425369fc
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
David Harris
bea6d0856d
Testbench directory cleanup
2022-01-07 17:02:16 +00:00
David Harris
120fb7863f
Reformatted MIT license to 95 characters
2022-01-07 12:58:40 +00:00
David Harris
85fa620cfb
Finished removing generate statements
2022-01-05 16:41:17 +00:00
David Harris
08e6a10480
Removed imperas mmu tests; using wallypriv instead
2022-01-04 23:14:53 +00:00
David Harris
b36ace221e
Renamed wally-pipelined to pipelined
2022-01-04 19:47:41 +00:00
