4 Commits

Author	SHA1	Message	Date
Ross Thompson	42ef1e22e5	1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU. ... 2. Removed the write address delay from simpleram.sv 3. Fixed rv32tim and rv32ic mode to handle missalignment correctly. 4. Added imperas32i and imperas32c to rv32tim mode.	2022-01-26 18:23:39 -06:00
David Harris	325724f556	LSU Cleanup	2022-01-15 01:11:17 +00:00
Ross Thompson	3bec276862	Added tim only test to regression-wally. Minor cleanup to ifu.	2022-01-14 11:13:06 -06:00
David Harris	54d852f6ae	renamed regression-wally.py to regression-wally	2022-01-07 17:47:38 +00:00