Ross Thompson
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d50a65720d
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More name cleanup in caches.
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2021-12-30 09:18:16 -06:00 |
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Ross Thompson
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d474caf24f
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Removed WAdr from cacheway as it is redundant.
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2021-12-29 21:39:43 -06:00 |
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Ross Thompson
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c4170ece27
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Replaced async reset flip flops with sync reset flip flops in cache and bpread.
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2021-10-27 09:57:11 -05:00 |
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David Harris
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426a43f77b
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Forgot to save cacheway merge
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2021-10-26 08:38:13 -07:00 |
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David Harris
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c0145c0a35
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merging changes
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2021-10-26 08:34:36 -07:00 |
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David Harris
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8287a1ef3e
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Synchronous reset in non-flop blocks
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2021-10-26 08:30:35 -07:00 |
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Ross Thompson
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c43b19120f
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Fixed another critical path in the caches.
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2021-10-25 22:05:11 -05:00 |
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Ross Thompson
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8a51fe76c1
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Partial cleanup of unused signals in caches and bpred.
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2021-10-24 15:04:20 -05:00 |
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Ross Thompson
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cd58a388e4
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fixed issues with dc shell not liking modules with parameters without default values.
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2021-10-18 17:24:15 -05:00 |
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Ross Thompson
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0b1e59d075
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Updated Dcache to fully support flush. This appears to work.
Updated PCNextF so it points to the correct PC after icache invalidate.
Build root crashes with PCW mismatch and invalid register writes.
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2021-09-17 10:25:21 -05:00 |
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Ross Thompson
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615fd41e7b
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Added states and all control and data path logic to support d cache flush. This is currently untested; however the existing regresss test passes.
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2021-09-16 18:32:29 -05:00 |
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Ross Thompson
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d901f60a6d
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Added flush controls to cachway.
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2021-09-16 16:56:48 -05:00 |
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Ross Thompson
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cae350abb7
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Added invalidate to icache.
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2021-09-16 16:15:54 -05:00 |
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Ross Thompson
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6965bde95c
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
Refixed some bit width issues in the icache.
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2021-09-09 12:44:02 -05:00 |
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Ross Thompson
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1d370ca71f
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fixed some lint bugs.
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2021-09-09 12:38:57 -05:00 |
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David Harris
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12bd351edf
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Lint cleaning, riscv-arch-test testing
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2021-09-09 11:05:12 -04:00 |
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Ross Thompson
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d6ff89b7e6
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Swapped out the icachemem for cacheway. cacheway is modified to optionally support dirty bits.
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2021-08-26 15:43:02 -05:00 |
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Ross Thompson
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d23b860c96
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Moved LRU and storage for the LRU into a single module. Also found a subtle bug with the update address used to write the cache's memory.
This was correct for the LRU but incorrect for the data, tag, valid, and dirty storage.
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2021-08-25 21:09:42 -05:00 |
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Ross Thompson
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c5e2443298
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Replaced dcache generate ORing with or_rows.
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2021-08-25 13:46:36 -05:00 |
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Ross Thompson
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e5336f4ee1
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Rename of DCacheMem to cacheway.
simplified dcache names.
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2021-08-25 13:33:15 -05:00 |
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