3 Commits

Author	SHA1	Message	Date
Ross Thompson	a4907b5d29	Lee Moore found another bug using imperas. ... An ITLB miss concurrent with a d cache flush did not interlock. The LSU should suppress the d cache flush until the hptw fills the missing tlb entry.	2023-02-02 23:52:21 -06:00
Ross Thompson	0530d3fca3	Test commit. please merge.	2023-01-23 12:53:31 -06:00
Ross Thompson	1c83914662	Fixed bug. ... It was possible for DTLBMissM to prevent a dcache flush.	2022-02-11 14:00:01 -06:00