switched comparator to dc flip version

pipelined/src/ieu/comparator.sv

@@ -80,7 +80,7 @@ module comparator #(parameter WIDTH=64) (
   assign flags = {eq, lt, ltu};
 endmodule
 
-// This comaprator is best
+// This comparator is best
 module comparator_dc_flip #(parameter WIDTH=64) (
   input  logic [WIDTH-1:0] a, b,
   input  logic             sgnd,
@@ -94,7 +94,7 @@ module comparator_dc_flip #(parameter WIDTH=64) (
   assign bf = {b[WIDTH-1] ^ sgnd, b[WIDTH-2:0]};
 
   // behavioral description gives best results
-  assign eq = (af == bf);
+  assign eq = (a == b);
   assign lt = (af < bf);
   assign flags = {eq, lt};
 endmodule

pipelined/src/ieu/controller.sv

@@ -41,7 +41,7 @@ module controller(
   output logic       IllegalBaseInstrFaultD,
   // Execute stage control signals
   input logic 	     StallE, FlushE,  
-  input logic  [2:0] FlagsE, 
+  input logic  [1:0] FlagsE, 
   input  logic       FWriteIntE,
   output logic       PCSrcE,        // for datapath and Hazard Unit
   output logic [2:0] ALUControlE, 
@@ -52,6 +52,7 @@ module controller(
   output logic       MDUE, W64E,
   output logic       JumpE,	
   output logic       SCE,
+  output logic       BranchSignedE,
   // Memory stage control signals
   input  logic       StallM, FlushM,
   output logic [1:0] MemRWM,
@@ -211,8 +212,9 @@ module controller(
                            {IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FencePendingE, InstrValidE});
 
   // Branch Logic
-  assign {eqE, ltE, ltuE} = FlagsE;
-  mux4 #(1) branchflagmux(eqE, 1'b0, ltE, ltuE, Funct3E[2:1], BranchFlagE);
+  assign BranchSignedE = ~(Funct3E[2:1] == 2'b11);
+  assign {eqE, ltE} = FlagsE;
+  mux3 #(1) branchflagmux(eqE, 1'b0, ltE, Funct3E[2:1], BranchFlagE);
   assign BranchTakenE = BranchFlagE ^ Funct3E[0];
   assign PCSrcE = JumpE | BranchE & BranchTakenE;
 

pipelined/src/ieu/datapath.sv

@@ -43,11 +43,12 @@ module datapath (
   input  logic             ALUSrcAE, ALUSrcBE,
   input  logic             ALUResultSrcE, 
   input  logic             JumpE,
+  input  logic             BranchSignedE,
   input  logic             IllegalFPUInstrE,
   input  logic [`XLEN-1:0] FWriteDataE,
   input  logic [`XLEN-1:0] PCE,
   input  logic [`XLEN-1:0] PCLinkE,
-  output logic [2:0]       FlagsE,
+  output logic [1:0]       FlagsE,
   output logic [`XLEN-1:0] IEUAdrE,
   output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
   // Memory stage signals
@@ -106,7 +107,7 @@ module datapath (
 	
   mux3  #(`XLEN)  faemux(R1E, ResultW, IFResultM, ForwardAE, ForwardedSrcAE);
   mux3  #(`XLEN)  fbemux(R2E, ResultW, IFResultM, ForwardBE, ForwardedSrcBE);
-  comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, FlagsE);
+  comparator_dc_flip #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE);
   mux2  #(`XLEN)  srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE);
   mux2  #(`XLEN)  srcbmux(ForwardedSrcBE, ExtImmE, ALUSrcBE, SrcBE);
   alu   #(`XLEN)  alu(SrcAE, SrcBE, ALUControlE, Funct3E, ALUResultE, IEUAdrE);

pipelined/src/ieu/ieu.sv

@@ -78,7 +78,7 @@ module ieu (
 );
 
   logic [2:0]  ImmSrcD;
-  logic [2:0]  FlagsE;
+  logic [1:0]  FlagsE;
   logic [2:0]  ALUControlE;
   logic        ALUSrcAE, ALUSrcBE;
   logic [2:0]  ResultSrcW;
@@ -93,19 +93,20 @@ module ieu (
   logic             RegWriteM, RegWriteW;
   logic             MemReadE, CSRReadE;
   logic             JumpE;
+  logic             BranchSignedE;
            
   controller c(
     .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD,
     .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, .StallE, .FlushE, .FlagsE, .FWriteIntE,
     .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .MemReadE, .CSRReadE, 
-    .Funct3E, .MDUE, .W64E, .JumpE, .StallM, .FlushM, .MemRWM,
-    .CSRReadM, .CSRWriteM, .PrivilegedM, .SCE, .AtomicM, .Funct3M,
+    .Funct3E, .MDUE, .W64E, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM,
+    .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M,
     .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .FWriteIntM,
     .StallW, .FlushW, .RegWriteW, .ResultSrcW, .CSRWriteFencePendingDEM, .StoreStallD);
 
   datapath   dp(
     .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE,
-    .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .JumpE, .IllegalFPUInstrE,
+    .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .JumpE, .BranchSignedE, .IllegalFPUInstrE,
     .FWriteDataE, .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, 
     .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataE, .FResSelW,
     .StallW, .FlushW, .RegWriteW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW,