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Added 32 bit privilege tests that work but for one bug

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This commit is contained in:
Kip Macsai-Goren 2022-04-20 17:32:29 +00:00
parent 8e72ace5ac
commit fe14b9f188
21 changed files with 4684 additions and 344 deletions
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1024
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-MIE-01.reference_output Normal file
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-PIE-stack-01.reference_output Normal file
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-PIE-stack-s-01.reference_output Normal file
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15
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mtvec-01.reference_output
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@ -1,11 +1,10 @@
000000 00000aaa # Test 5.3.1.5: readback value of SIE after enabling all interrupts.
deadbeef 80000007 # mcause from m time interrupt
deadbeef 00000000 # mtval for mtime interrupt (0x0)
deadbeef 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
deadbeef 0000000b # mcause from M mode ecall from test termination
deadbeef 00000000 # mtval of ecall (*** defined to be zero for now)
deadbeef 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
deadbeef
deadbeef deadbeef
deadbeef deadbeef
deadbeef deadbeef

4
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-scratch-01.reference_output
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@ -1,7 +1,7 @@
00000111 # Test 5.3.2.3: successful read the 0x111 written to mscratch 00000111 # Test 5.3.2.3: successful read the 0x111 written to mscratch
00000000
0000000b # ecall from ending tests in machine mode 0000000b # ecall from ending tests in machine mode
deadbeef 00000000
deadbeef
deadbeef deadbeef
deadbeef deadbeef
deadbeef deadbeef

8
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-sscratch-s-01.reference_output
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@ -1,11 +1,11 @@
00000111 # Test 5.3.2.3: successful read of the 0x111 written to sscratch 00000111 # Test 5.3.2.3: successful read of the 0x111 written to sscratch
00000000
0000000b # ecall from going to s mode from m mode 0000000b # ecall from going to s mode from m mode
00000000
00000aaa # successful read of 0xAAA written to sscratch 00000aaa # successful read of 0xAAA written to sscratch
00000000
00000009 # ecall from ending tests in supervisor mode 00000009 # ecall from ending tests in supervisor mode
deadbeef 00000000
deadbeef
deadbeef
deadbeef
deadbeef deadbeef
deadbeef deadbeef
deadbeef deadbeef

40
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-stvec-01.reference_output
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@ -1,23 +1,23 @@
deadbeef 00000aaa # Test 5.3.1.5: readback value of MIE after enabling all interrupts.
deadbeef 00000222 # readback value of mideleg after attempting to delegate all interrupts.
deadbeef 0000000b # mcause from ecall for going from M mode to S mode
deadbeef 00000000 # mtval of ecall (*** defined to be zero for now)
deadbeef 00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 80000001 # mcause from s soft interrupt
deadbeef 00000000 # mtval for ssoft interrupt (0x0)
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000009 # mcause from ecall for going from S mode to M mode
deadbeef 00000000 # mtval of ecall (*** defined to be zero for now)
deadbeef 00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 0000000b # mcause from ecall for going from M mode to U mode
deadbeef 00000000 # mtval of ecall (*** defined to be zero for now)
deadbeef 00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 80000001 # mcause from s soft interrupt from user mode this time
deadbeef 00000000 # mtval for mtime interrupt (0x0)
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000008 # mcause from U mode ecall from test termination
deadbeef 00000000 # mtval of ecall (*** defined to be zero for now)
deadbeef 00000000 # masked out mstatus.MPP = 00, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef deadbeef
deadbeef deadbeef
deadbeef deadbeef

76
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output
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@ -1,4 +1,7 @@
00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts 00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts
00000000 # mcause from instruction addr misaligned fault
8000013a # mtval of faulting instruction adress
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000001 # mcause from an instruction access fault 00000001 # mcause from an instruction access fault
00000000 # mtval of faulting instruction address (0x0) 00000000 # mtval of faulting instruction address (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
@ -6,16 +9,16 @@
00000000 # mtval of faulting instruction (0x0) 00000000 # mtval of faulting instruction (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000003 # mcause from Breakpoint 00000003 # mcause from Breakpoint
800003ec # mtval of breakpoint instruction adress (0x800003ec) 8000016c # mtval of breakpoint instruction adress
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000004 # mcause from load address misaligned 00000004 # mcause from load address misaligned
800003f5 # mtval of misaligned address (0x800003f5) 80000175 # mtval of misaligned address
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000005 # mcause from load access 00000005 # mcause from load access
00000000 # mtval of accessed adress (0x0) 00000000 # mtval of accessed adress (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000006 # mcause from store misaligned 00000006 # mcause from store misaligned
80000411 # mtval of address with misaligned store instr (0x80000410) 80000191 # mtval of address with misaligned store instr
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000007 # mcause from store access 00000007 # mcause from store access
00000000 # mtval of accessed address (0x0) 00000000 # mtval of accessed address (0x0)
@ -29,37 +32,52 @@
00000009 # mcause from S mode ecall 00000009 # mcause from S mode ecall
00000000 # mtval of ecall (*** defined to be zero for now) 00000000 # mtval of ecall (*** defined to be zero for now)
00000880 # masked out mstatus.MPP = 01 (from S mode), mstatus.MPIE = 1, and mstatus.MIE = 0 00000880 # masked out mstatus.MPP = 01 (from S mode), mstatus.MPIE = 1, and mstatus.MIE = 0
000007ec # value to indicate a vectored interrupts 0007ec01 # value to indicate successful vectoring on s soft interrupt
80000001 # mcause value from s soft interrupt
00000000 # mtval for ssoft interrupt (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
0007ec03 # value to indicate successful vectoring on m soft interrupt
80000003 # mcause value from m soft interrupt
00000000 # mtval for msoft interrupt (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
0007ec05 # value to indicate successful vectoring on s time interrupt
80000005 # mcause value from s time interrupt
00000000 # mtval for stime interrupt (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
0007ec07 # value to indicate successful vectoring on m time interrupt
80000007 # mcause value from m time interrupt 80000007 # mcause value from m time interrupt
00000000 # mtval for mtime interrupt (0x0) 00000000 # mtval for mtime interrupt (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
000007ec # value to indicate a vectored interrupts 0007ec09 # value to indicate successful vectoring on s ext interrupt
80000001 # mcause value from m soft interrupt 80000009 # mcause value from s ext interrupt
00000000 # mtval for msoft interrupt (0x0) 00000000 # mtval for sext interrupt (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
000007ec # value to indicate a vectored interrupts 0007ec0b # value to indicate successful vectoring on m ext interrupt
8000000b # mcause value from m ext interrupt 8000000b # mcause value from m ext interrupt
00000000 # mtval for mext interrupt (0x0) 00000000 # mtval for mext interrupt (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
0000b309 # medeleg after attempted write of all 1's (only some bits are writeable) fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
00000222 # mideleg after attempted write of all 1's (only some bits are writeable) 00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
00000001 # Test 5.3.1.4: mcause from an instruction access fault 00000000 # mcause from instruction addr misaligned fault
8000013a # mtval of faulting instruction adress
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000001 # mcause from an instruction access fault
00000000 # mtval of faulting instruction address (0x0) 00000000 # mtval of faulting instruction address (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000002 # mcause from an Illegal instruction 00000002 # mcause from an Illegal instruction
00000000 # mtval of faulting instruction (0x0) 00000000 # mtval of faulting instruction (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000003 # mcause from Breakpoint 00000003 # mcause from Breakpoint
800003ec # mtval of breakpoint instruction adress (0x800003ec) 8000016c # mtval of breakpoint instruction adress
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000004 # mcause from load address misaligned 00000004 # mcause from load address misaligned
800003f5 # mtval of misaligned address (0x800003f5) 80000175 # mtval of misaligned address
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000005 # mcause from load access 00000005 # mcause from load access
00000000 # mtval of accessed adress (0x0) 00000000 # mtval of accessed adress (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000006 # mcause from store misaligned 00000006 # mcause from store misaligned
80000411 # mtval of address with misaligned store instr (0x80000410) 80000191 # mtval of address with misaligned store instr
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000007 # mcause from store access 00000007 # mcause from store access
00000000 # mtval of accessed address (0x0) 00000000 # mtval of accessed address (0x0)
@ -67,16 +85,16 @@
0000000b # mcause from M mode ecall 0000000b # mcause from M mode ecall
00000000 # mtval of ecall (*** defined to be zero for now) 00000000 # mtval of ecall (*** defined to be zero for now)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
000007ec # value to indicate a vectored interrupts 0007ec03 # value to indicate successful vectoring on m soft interrupt
80000007 # mcause value from time interrupt 80000003 # mcause value from m soft interrupt
00000000 # mtval for mtime interrupt (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
000007ec # value to indicate a vectored interrupts
80000001 # mcause value from m soft interrupt
00000000 # mtval for msoft interrupt (0x0) 00000000 # mtval for msoft interrupt (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
000007ec # value to indicate a vectored interrupts 0007ec07 # value to indicate successful vectoring on m time interrupt
0000000b # mcause value from m ext interrupt 80000007 # mcause value from m time interrupt
00000000 # mtval for mtime interrupt (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
0007ec0b # value to indicate successful vectoring on m ext interrupt
8000000b # mcause value from m ext interrupt
00000000 # mtval for mext interrupt (0x0) 00000000 # mtval for mext interrupt (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
0000000b # mcause from M mode ecall from test termination 0000000b # mcause from M mode ecall from test termination
@ -988,3 +1006,19 @@ deadbeef
deadbeef deadbeef
deadbeef deadbeef
deadbeef deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef

206
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output
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@ -1,106 +1,106 @@
deadbeef 00000aaa # readback value from writing mie to enable interrupts
deadbeef 0000000b # Test 5.3.1.4: mcause from ecall going from M mode to S mode
deadbeef 00000000 # mtval of ecall (*** defined to be zero for now)
deadbeef 00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000 # scause from instruction addr misaligned fault
deadbeef 8000013a # stval of faulting instruction adress
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000001 # scause from an instruction access fault
deadbeef 00000000 # stval of faulting instruction address (0x0)
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000002 # scause from an Illegal instruction
deadbeef 00000000 # stval of faulting instruction (0x0)
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000003 # scause from Breakpoint
deadbeef 8000016c # stval of breakpoint instruction adress
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000004 # scause from load address misaligned
deadbeef 80000175 # stval of misaligned address
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000005 # scause from load access
deadbeef 00000000 # stval of accessed adress (0x0)
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000006 # scause from store misaligned
deadbeef 80000191 # stval of address with misaligned store instr
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000007 # scause from store access
deadbeef 00000000 # stval of accessed address (0x0)
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000009 # scause from S mode ecall
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000008 # scause from U mode ecall
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000000 # masked out mstatus.mpp = 0 (from U mode), mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 0007ec01 # value to indicate successful vectoring on s soft interrupt
deadbeef 80000001 # scause value from s soft interrupt
deadbeef 00000000 # stval for ssoft interrupt (0x0)
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 0007ec03 # value to indicate successful vectoring on m soft interrupt
deadbeef 80000003 # scause value from m soft interrupt
deadbeef 00000000 # stval for msoft interrupt (0x0)
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 0007ec07 # value to indicate successful vectoring on m time interrupt
deadbeef 80000007 # scause value from m time interrupt
deadbeef 00000000 # stval for mtime interrupt (0x0)
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 0007ec09 # value to indicate successful vectoring on s ext interrupt
deadbeef 80000009 # scause value from s ext interrupt
deadbeef 00000000 # stval for sext interrupt (0x0)
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 0007ec0b # value to indicate successful vectoring on m ext interrupt
deadbeef 8000000b # scause value from m ext interrupt
deadbeef 00000000 # stval for mext interrupt (0x0)
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000009 # scause from S mode ecall
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
deadbeef 00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
deadbeef 0000000b # scause from M mode ecall
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000 # scause from instruction addr misaligned fault
deadbeef 8000013a # stval of faulting instruction adress
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000001 # scause from an instruction access fault
deadbeef 00000000 # stval of faulting instruction address (0x0)
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000002 # scause from an Illegal instruction
deadbeef 00000000 # stval of faulting instruction (0x0)
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000003 # scause from Breakpoint
deadbeef 8000016c # stval of breakpoint instruction adress
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000004 # scause from load address misaligned
deadbeef 80000175 # stval of misaligned address
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000005 # scause from load access
deadbeef 00000000 # stval of accessed adress (0x0)
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000006 # scause from store misaligned
deadbeef 80000191 # stval of address with misaligned store instr
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000007 # scause from store access
deadbeef 00000000 # stval of accessed address (0x0)
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000009 # scause from S mode ecall
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000008 # scause from U mode ecall
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 0007ec01 # value to indicate successful vectoring on s soft interrupt
deadbeef 80000001 # scause value from s soft interrupt
deadbeef 00000000 # stval for ssoft interrupt (0x0)
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 0007ec09 # value to indicate successful vectoring on s ext interrupt
deadbeef 80000009 # scause value from s ext interrupt
deadbeef 00000000 # stval for sext interrupt (0x0)
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000009 # scause from S mode ecall from test termination
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef deadbeef
deadbeef deadbeef
deadbeef deadbeef

1024
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-sret-01.reference_output Normal file
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@ -1,92 +1,92 @@
deadbeef 00000aaa # readback value from writing mie to enable interrupts
deadbeef 0000000b # Test 5.3.1.4: mcause from ecall going from M mode to U mode
deadbeef 00000000 # mtval of ecall (*** defined to be zero for now)
deadbeef 00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000 # scause from instruction addr misaligned fault
deadbeef 8000013a # stval of faulting instruction adress
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000001 # scause from an instruction access fault
deadbeef 00000000 # stval of faulting instruction address (0x0)
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000002 # scause from an Illegal instruction
deadbeef 00000000 # stval of faulting instruction (0x0)
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000003 # scause from Breakpoint
deadbeef 8000016c # stval of breakpoint instruction adress
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000004 # scause from load address misaligned
deadbeef 80000175 # stval of misaligned address
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000005 # scause from load access
deadbeef 00000000 # stval of accessed adress (0x0)
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000006 # scause from store misaligned
deadbeef 80000191 # stval of address with misaligned store instr
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000007 # scause from store access
deadbeef 00000000 # stval of accessed address (0x0)
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000008 # scause from U mode ecall
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000000 # masked out mstatus.mpp = 0 (from U mode), mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 0007ec03 # value to indicate successful vectoring on m soft interrupt
deadbeef 80000003 # scause value from m soft interrupt
deadbeef 00000000 # stval for msoft interrupt (0x0)
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 0007ec07 # value to indicate successful vectoring on m time interrupt
deadbeef 80000007 # scause value from m time interrupt
deadbeef 00000000 # stval for mtime interrupt (0x0)
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 0007ec09 # value to indicate successful vectoring on s ext interrupt
deadbeef 80000009 # scause value from s ext interrupt
deadbeef 00000000 # stval for sext interrupt (0x0)
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 0007ec0b # value to indicate successful vectoring on m ext interrupt
deadbeef 8000000b # scause value from m ext interrupt
deadbeef 00000000 # stval for mext interrupt (0x0)
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000008 # scause from U mode ecall
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
deadbeef 00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
deadbeef 0000000b # scause from M mode ecall
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000 # scause from instruction addr misaligned fault
deadbeef 8000013a # stval of faulting instruction adress
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000001 # scause from an instruction access fault
deadbeef 00000000 # stval of faulting instruction address (0x0)
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000002 # scause from an Illegal instruction
deadbeef 00000000 # stval of faulting instruction (0x0)
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000003 # scause from Breakpoint
deadbeef 8000016c # stval of breakpoint instruction adress
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000004 # scause from load address misaligned
deadbeef 80000175 # stval of misaligned address
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000005 # scause from load access
deadbeef 00000000 # stval of accessed adress (0x0)
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000006 # scause from store misaligned
deadbeef 80000191 # stval of address with misaligned store instr
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000007 # scause from store access
deadbeef 00000000 # stval of accessed address (0x0)
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000008 # scause from U mode ecall
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 0007ec09 # value to indicate successful vectoring on s ext interrupt
deadbeef 80000009 # scause value from s ext interrupt
deadbeef 00000000 # stval for sext interrupt (0x0)
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000008 # scause from U mode ecall from test termination
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef deadbeef
deadbeef deadbeef
deadbeef deadbeef

44
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-MIE-01.S Normal file
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@ -0,0 +1,44 @@
///////////////////////////////////////////
//
// WALLY-MIE
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2022-04-10
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "WALLY-TEST-LIB-32.h"
INIT_TESTS
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
li x28, 0x8
csrs mstatus, x28 // set mstatus.MIE bit to 1.
WRITE_READ_CSR mie, 0x0 // force zeroing out mie CSR.
// test 5.3.1.6 Interrupt enabling and priority tests
// note that none of these interrupts should be caught or handled.
jal cause_m_soft_interrupt
END_TESTS
TEST_STACK_AND_DATA

49
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PIE-stack-01.S Normal file
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@ -0,0 +1,49 @@
///////////////////////////////////////////
//
// WALLY-privilege-interrupt-enable-stack
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2022-04-10
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "WALLY-TEST-LIB-32.h"
INIT_TESTS
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
TRAP_HANDLER m, DEBUG=1
li x28, 0x8
csrs mstatus, x28 // set mstatus.MIE bit to 1
WRITE_READ_CSR mie, 0xFFF
// test 5.3.1.6 Interrupt enabling and priority tests
// Cause interrupt, ensuring that status.mie = 0 , status.mpie = 1, and status.mpp = 11 during trap handling
jal cause_m_soft_interrupt // *** only cause one interrupt because we just want to test the status stack
li x28, 0x8
csrc mstatus, x28 // set mstatus.MIE bit to 0. interrupts from M mode should not happen
// attempt to cause interrupt, it should not go through
jal cause_m_soft_interrupt
END_TESTS
TEST_STACK_AND_DATA

53
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PIE-stack-s-01.S Normal file
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@ -0,0 +1,53 @@
///////////////////////////////////////////
//
// WALLY-privilege-interrupt-enable-stack
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2022-04-10
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "WALLY-TEST-LIB-32.h"
INIT_TESTS
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
TRAP_HANDLER m, DEBUG=1 // necessary so we can go to S mode
TRAP_HANDLER s, DEBUG=1 // neccessary to handle s mode interrupts.
li x28, 0x2
csrs sstatus, x28 // set sstatus.SIE bit to 1
WRITE_READ_CSR mie, 0xFFF // enable all interrupts, including supervisor ones
WRITE_READ_CSR mideleg 0xFFFF // delegate all interrupts to S mode.
// test 5.3.1.6 Interrupt enabling and priority tests
GOTO_S_MODE
// Cause interrupt, ensuring that status.sie = 0 , status.spie = 1, and status.spp = 1 during trap handling
jal cause_s_soft_interrupt // *** only cause one interrupt because we just want to test the status stack
li x28, 0x2
csrc sstatus, x28 // set sstatus.SIE bit to 0. interrupts from S mode should not happen
// attempt to cause interrupt, it should not go through
jal cause_s_soft_interrupt
END_TESTS
TEST_STACK_AND_DATA

13
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S
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@ -21,24 +21,23 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/////////////////////////////////////////// ///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h" #include "WALLY-TEST-LIB-32.h"
INIT_TESTS INIT_TESTS
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
// test 5.3.1.5 Unvectored interrupt tests // test 5.3.1.5 Unvectored interrupt tests
TRAP_HANDLER m, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits. TRAP_HANDLER m, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits.
li x28, 0x8 li x28, 0x8
csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode csrs mstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode
WRITE_READ_CSR mie, 0xFFF // *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts WRITE_READ_CSR mie, 0xFFF
// cause traps, ensuring that we DONT go through the vectored part of the trap handler // cause traps, ensuring that we DONT go through the vectored part of the trap handler
// *** this assumes that interrupt code 0 remains reserved
CAUSE_TIME_INTERRUPT // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. jal cause_m_time_interrupt // *** only cause one interrupt because we just want to test the status stack
CAUSE_SOFT_INTERRUPT // *** exiting out of the trap handler after these is current;y broken
CAUSE_EXT_INTERRUPT
END_TESTS END_TESTS

1
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-scratch-01.S
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@ -26,7 +26,6 @@
INIT_TESTS INIT_TESTS
TRAP_HANDLER m TRAP_HANDLER m
// Test 5.3.2.3: Scratch registers test // Test 5.3.2.3: Scratch registers test
WRITE_READ_CSR mscratch, 0x111 // check that mscratch is readable and writeable in machine mode WRITE_READ_CSR mscratch, 0x111 // check that mscratch is readable and writeable in machine mode

27
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S
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@ -21,34 +21,33 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/////////////////////////////////////////// ///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h" #include "WALLY-TEST-LIB-32.h"
INIT_TESTS INIT_TESTS
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
// test 5.3.1.5 Unvectored interrupt tests // test 5.3.1.5 Unvectored interrupt tests
TRAP_HANDLER m, VECTORED=0, DEBUG=1 // necessary to handle changing modes
TRAP_HANDLER s, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits. TRAP_HANDLER s, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits.
// li x28, 0x8 li x28, 0x2
// csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode csrs sstatus, x28 // set sstatus.SIE bit to 1
// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts WRITE_READ_CSR mie, 0xFFFF
WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
// cause traps, ensuring that we DONT go through the vectored part of the trap handler
GOTO_S_MODE GOTO_S_MODE
// cause traps, ensuring that we DONT go through the vectored part of the trap handler jal cause_s_soft_interrupt // *** only cause one interrupt since we just want to test the tvec csr
// *** this assumes that interrupt code 0 remains reserved
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. GOTO_M_MODE
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
// CAUSE_EXT_INTERRUPT
GOTO_U_MODE jal cause_s_soft_interrupt // set software interrupt pending without it firing so we can make it fire in U mode
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. GOTO_U_MODE // Should cause software interrupt to fire off.
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
// CAUSE_EXT_INTERRUPT
END_TESTS END_TESTS

30
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S
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@ -21,7 +21,7 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/////////////////////////////////////////// ///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h" #include "WALLY-TEST-LIB-32.h"
INIT_TESTS INIT_TESTS
@ -35,7 +35,7 @@ WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources // *** commented
// test 5.3.1.4 Basic trap tests // test 5.3.1.4 Basic trap tests
// jal cause_instr_addr_misaligned //skipped becuase this exception may be impossible when compressed instructions are enabled) jal cause_instr_addr_misaligned
jal cause_instr_access jal cause_instr_access
jal cause_illegal_instr jal cause_illegal_instr
jal cause_breakpnt jal cause_breakpnt
@ -47,16 +47,21 @@ GOTO_U_MODE // Causes M mode ecall
GOTO_S_MODE // Causes U mode ecall GOTO_S_MODE // Causes U mode ecall
GOTO_M_MODE // Causes S mode ecall GOTO_M_MODE // Causes S mode ecall
jal cause_time_interrupt // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
jal cause_soft_interrupt // *** exiting out of the trap handler after these is current;y broken jal cause_s_soft_interrupt
jal cause_ext_interrupt jal cause_m_soft_interrupt
jal cause_s_time_interrupt
jal cause_m_time_interrupt
jal cause_s_ext_interrupt_GPIO
jal cause_m_ext_interrupt
// try the traps again with mideleg = medeleg = all 1's to ensure traps still go to M mode from M mode // try the traps again with mideleg = medeleg = all 1's to ensure traps still go to M mode from M mode
WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF
WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
// jal cause_instr_addr_misaligned //skipped becuase this exception may be impossible when compressed instructions are enabled) jal cause_instr_addr_misaligned
jal cause_instr_access jal cause_instr_access
jal cause_illegal_instr jal cause_illegal_instr
jal cause_breakpnt jal cause_breakpnt
@ -66,9 +71,16 @@ jal cause_store_addr_misaligned
jal cause_store_acc jal cause_store_acc
jal cause_ecall // M mode ecall jal cause_ecall // M mode ecall
jal cause_time_interrupt // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. jal cause_s_soft_interrupt // The delegated S mode interrupts should not fire since we're running in M mode.
jal cause_soft_interrupt // *** exiting out of the trap handler after these is current;y broken jal cause_m_soft_interrupt
jal cause_ext_interrupt jal cause_s_time_interrupt
jal cause_m_time_interrupt
li a3, 0x40 // these interrupts involve a time loop waiting for the interrupt to go off.
// since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3
jal cause_s_ext_interrupt_GPIO
li a3, 0x40
jal cause_m_ext_interrupt
END_TESTS END_TESTS

78
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S
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@ -21,38 +21,46 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/////////////////////////////////////////// ///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h" #include "WALLY-TEST-LIB-32.h"
INIT_TESTS INIT_TESTS
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
// test 5.3.1.4 Basic trap tests // test 5.3.1.4 Basic trap tests
TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps TRAP_HANDLER m, DEBUG=1 // necessary to handle switching privilege modes
TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well
// Like WALLY-trap, cause all the same traps from S mode and make sure they go to machine mode with zeroed mideleg, medeleg // Like WALLY-trap, cause all the same traps from S mode and make sure they go to machine mode with zeroed mideleg, medeleg
li x28, 0x2
csrs sstatus, x28 // set sstatus.SIE bit to 1
WRITE_READ_CSR mie, 0xFFFF // sie is a subset of mie, so writing this also enables sie.
GOTO_S_MODE GOTO_S_MODE
li x28, 0x8 jal cause_instr_addr_misaligned
csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode jal cause_instr_access
// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts jal cause_illegal_instr
jal cause_breakpnt
jal cause_load_addr_misaligned
jal cause_load_acc
jal cause_store_addr_misaligned
jal cause_store_acc
GOTO_U_MODE // Causes S mode ecall
GOTO_S_MODE // Causes U mode ecall
// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) jal cause_s_soft_interrupt
CAUSE_INSTR_ACCESS jal cause_m_soft_interrupt
CAUSE_ILLEGAL_INSTR //jal cause_s_time_interrupt // *** S time interrupts cannot come from S mode as of 4/19/22.
CAUSE_BREAKPNT jal cause_m_time_interrupt
CAUSE_LOAD_ADDR_MISALIGNED li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off.
CAUSE_LOAD_ACC // since interrupts are not always enabled,
CAUSE_STORE_ADDR_MISALIGNED jal cause_s_ext_interrupt_GPIO
CAUSE_STORE_ACC li a3, 0x40
CAUSE_ECALL jal cause_m_ext_interrupt
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
// CAUSE_EXT_INTERRUPT
// Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler // Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler
// We can tell which one becuase the different trap handler modes write different bits of the status register // We can tell which one becuase the different trap handler modes write different bits of the status register
@ -63,21 +71,27 @@ GOTO_M_MODE // so we can write the delegate registers
WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF
WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
GOTO_S_MODE GOTO_S_MODE // Since we're running in M mode, this ecall will NOT be delegated to S mode
// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) jal cause_instr_addr_misaligned
CAUSE_INSTR_ACCESS jal cause_instr_access
CAUSE_ILLEGAL_INSTR jal cause_illegal_instr
CAUSE_BREAKPNT jal cause_breakpnt
CAUSE_LOAD_ADDR_MISALIGNED jal cause_load_addr_misaligned
CAUSE_LOAD_ACC jal cause_load_acc
CAUSE_STORE_ADDR_MISALIGNED jal cause_store_addr_misaligned
CAUSE_STORE_ACC jal cause_store_acc
CAUSE_ECALL GOTO_U_MODE // Causes S mode ecall
GOTO_S_MODE // Causes U mode ecall
jal cause_s_soft_interrupt // *** M mode Interrupts cannot be delegated in this implementation
//jal cause_m_soft_interrupt
//jal cause_s_time_interrupt
//jal cause_m_time_interrupt
li a3, 0x40
jal cause_s_ext_interrupt_GPIO
//jal cause_m_ext_interrupt
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
// CAUSE_EXT_INTERRUPT
END_TESTS END_TESTS

42
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-sret-01.S Normal file
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@ -0,0 +1,42 @@
///////////////////////////////////////////
//
// WALLY-trap-sret
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2022-04-10
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "WALLY-TEST-LIB-32.h"
INIT_TESTS
TRAP_HANDLER m, DEBUG=1
// test 5.3.1.6 Interrupt enabling and priority tests
li x28, 0x400000
csrs mstatus, x28 // Set mstatus.tsr to 1.
GOTO_S_MODE
sret // attempt to run sret instruction.
// should cause illegal instruction exception despite being in s mode
END_TESTS
TEST_STACK_AND_DATA

74
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S
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@ -21,10 +21,12 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/////////////////////////////////////////// ///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h" #include "WALLY-TEST-LIB-32.h"
INIT_TESTS INIT_TESTS
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
// test 5.3.1.4 Basic trap tests // test 5.3.1.4 Basic trap tests
TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
@ -32,27 +34,31 @@ TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well
// Like WALLY-trap, cause all the same traps from U mode and make sure they go to machine mode with zeroed mideleg, medeleg // Like WALLY-trap, cause all the same traps from U mode and make sure they go to machine mode with zeroed mideleg, medeleg
li x28, 0x2
csrs sstatus, x28 // set sstatus.SIE bit to 1. Not strictly necessary but this lets us differentiate which trap handler we went to
WRITE_READ_CSR mie, 0xFFFF
GOTO_U_MODE GOTO_U_MODE
// li x28, 0x8 jal cause_instr_addr_misaligned
// csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode jal cause_instr_access
// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts jal cause_illegal_instr
jal cause_breakpnt
jal cause_load_addr_misaligned
// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) jal cause_load_acc
CAUSE_INSTR_ACCESS jal cause_store_addr_misaligned
CAUSE_ILLEGAL_INSTR jal cause_store_acc
CAUSE_BREAKPNT jal cause_ecall
CAUSE_LOAD_ADDR_MISALIGNED
CAUSE_LOAD_ACC
CAUSE_STORE_ADDR_MISALIGNED
CAUSE_STORE_ACC
CAUSE_ECALL
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
// CAUSE_EXT_INTERRUPT
//jal cause_s_soft_interrupt // *** writing SIP from u mode is illegal
jal cause_m_soft_interrupt
//jal cause_s_time_interrupt // *** S time interrupts cannot come from U mode as of 4/19/22.
jal cause_m_time_interrupt
li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off.
// since interrupts are not always enabled,
jal cause_s_ext_interrupt_GPIO
li a3, 0x40
jal cause_m_ext_interrupt
// Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler // Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler
// We can tell which one becuase the different trap handler modes write different bits of the status register // We can tell which one becuase the different trap handler modes write different bits of the status register
@ -65,19 +71,25 @@ WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
GOTO_U_MODE GOTO_U_MODE
// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) jal cause_instr_addr_misaligned
CAUSE_INSTR_ACCESS jal cause_instr_access
CAUSE_ILLEGAL_INSTR jal cause_illegal_instr
CAUSE_BREAKPNT jal cause_breakpnt
CAUSE_LOAD_ADDR_MISALIGNED jal cause_load_addr_misaligned
CAUSE_LOAD_ACC jal cause_load_acc
CAUSE_STORE_ADDR_MISALIGNED jal cause_store_addr_misaligned
CAUSE_STORE_ACC jal cause_store_acc
CAUSE_ECALL jal cause_ecall
//jal cause_s_soft_interrupt // *** S Soft interrupts cannot be caused from u mode since writing SIP is illegal
// *** M mode Interrupts cannot be delegated in this implementation
//jal cause_m_soft_interrupt
//jal cause_s_time_interrupt
//jal cause_m_time_interrupt
li a3, 0x40
jal cause_s_ext_interrupt_GPIO
//jal cause_m_ext_interrupt
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
// CAUSE_EXT_INTERRUPT
END_TESTS END_TESTS