Added generate around the longer latency version of the ram_ahb.sv

pipelined/src/uncore/ram_ahb.sv

@@ -29,6 +29,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
+`define RAM_LATENCY 0
 
 module ram_ahb #(parameter BASE=0, RANGE = 65535) (
   input  logic             HCLK, HRESETn, 
@@ -53,8 +54,6 @@ module ram_ahb #(parameter BASE=0, RANGE = 65535) (
   logic         nextHREADYRam;
   logic             DelayReady;
 
-  
-
   // a new AHB transactions starts when HTRANS requests a transaction, 
   // the peripheral is selected, and the previous transaction is completing
   assign initTrans = HREADY & HSELRam & HTRANS[1] ; 
@@ -78,37 +77,39 @@ module ram_ahb #(parameter BASE=0, RANGE = 65535) (
     memory(.clk(HCLK), .we(memwriteD), .bwe(HWSTRB), .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRam), .din(HWDATA));
 
   // use this to add arbitrary latency to ram. Helps test AHB controller correctness
-  logic [7:0]       NextCycle, Cycle;
+  if(`RAM_LATENCY > 0) begin
-  logic             CntEn, CntRst;
+    logic [7:0]       NextCycle, Cycle;
-  logic CycleFlag;
+    logic             CntEn, CntRst;
-  logic [7:0]       CycleThreshold;
+    logic             CycleFlag;
-  assign CycleThreshold = 0;
     
-  flopenr #(8) counter (HCLK, ~HRESETn | CntRst, CntEn, NextCycle, Cycle);
+    flopenr #(8) counter (HCLK, ~HRESETn | CntRst, CntEn, NextCycle, Cycle);
-  assign NextCycle = Cycle + 1'b1;
+    assign NextCycle = Cycle + 1'b1;
 
-  typedef enum logic  {READY, DELAY} statetype;
+    typedef enum      logic  {READY, DELAY} statetype;
-  statetype CurrState, NextState;
+    statetype CurrState, NextState;
     
-  always_ff @(posedge HCLK)
+    always_ff @(posedge HCLK)
-    if (~HRESETn)    CurrState <= #1 READY;
+      if (~HRESETn)    CurrState <= #1 READY;
-    else CurrState <= #1 NextState;  
+      else CurrState <= #1 NextState;  
 
-  always_comb begin
+    always_comb begin
-	case(CurrState)
+	  case(CurrState)
-	  READY: if(initTrans & ~CycleFlag) NextState = DELAY;
+	    READY: if(initTrans & ~CycleFlag) NextState = DELAY;
-                   else                          NextState = READY;
+        else                          NextState = READY;
-      DELAY: if(CycleFlag)                  NextState = READY;
+        DELAY: if(CycleFlag)                  NextState = READY;
-		           else                          NextState = DELAY;
+		else                          NextState = DELAY;
-	  default:                                      NextState = READY;
+	    default:                                      NextState = READY;
-	endcase
+	  endcase
+    end
+
+    assign CycleFlag = Cycle == `RAM_LATENCY;
+    assign CntEn = NextState == DELAY;
+    assign DelayReady = NextState == DELAY;
+    assign CntRst = NextState == READY;
+  end else begin
+    assign DelayReady = 0;
   end
   
-  assign CycleFlag = Cycle == CycleThreshold;
-  assign CntEn = NextState == DELAY;
-  assign DelayReady = NextState == DELAY;
-  assign CntRst = NextState == READY;
-  
   
 endmodule