Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Added generate around the longer latency version of the ram_ahb.sv

Browse Source
This commit is contained in:
Ross Thompson 2022-09-06 09:21:03 -05:00
parent 20842b38b9
commit fcf72bb6ba
1 changed files with 30 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
pipelined/src/uncore/ram_ahb.sv
View File

@ -29,6 +29,7 @@
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
`include "wally-config.vh" `include "wally-config.vh"
`define RAM_LATENCY 0
module ram_ahb #(parameter BASE=0, RANGE = 65535) ( module ram_ahb #(parameter BASE=0, RANGE = 65535) (
input logic HCLK, HRESETn, input logic HCLK, HRESETn,
@ -53,8 +54,6 @@ module ram_ahb #(parameter BASE=0, RANGE = 65535) (
logic nextHREADYRam; logic nextHREADYRam;
logic DelayReady; logic DelayReady;
// a new AHB transactions starts when HTRANS requests a transaction, // a new AHB transactions starts when HTRANS requests a transaction,
// the peripheral is selected, and the previous transaction is completing // the peripheral is selected, and the previous transaction is completing
assign initTrans = HREADY & HSELRam & HTRANS[1] ; assign initTrans = HREADY & HSELRam & HTRANS[1] ;
@ -78,11 +77,10 @@ module ram_ahb #(parameter BASE=0, RANGE = 65535) (
memory(.clk(HCLK), .we(memwriteD), .bwe(HWSTRB), .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRam), .din(HWDATA)); memory(.clk(HCLK), .we(memwriteD), .bwe(HWSTRB), .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRam), .din(HWDATA));
// use this to add arbitrary latency to ram. Helps test AHB controller correctness // use this to add arbitrary latency to ram. Helps test AHB controller correctness
if(`RAM_LATENCY > 0) begin
logic [7:0] NextCycle, Cycle; logic [7:0] NextCycle, Cycle;
logic CntEn, CntRst; logic CntEn, CntRst;
logic CycleFlag; logic CycleFlag;
logic [7:0] CycleThreshold;
assign CycleThreshold = 0;
flopenr #(8) counter (HCLK, ~HRESETn | CntRst, CntEn, NextCycle, Cycle); flopenr #(8) counter (HCLK, ~HRESETn | CntRst, CntEn, NextCycle, Cycle);
assign NextCycle = Cycle + 1'b1; assign NextCycle = Cycle + 1'b1;
@ -104,10 +102,13 @@ module ram_ahb #(parameter BASE=0, RANGE = 65535) (
endcase endcase
end end
assign CycleFlag = Cycle == CycleThreshold; assign CycleFlag = Cycle == `RAM_LATENCY;
assign CntEn = NextState == DELAY; assign CntEn = NextState == DELAY;
assign DelayReady = NextState == DELAY; assign DelayReady = NextState == DELAY;
assign CntRst = NextState == READY; assign CntRst = NextState == READY;
end else begin
assign DelayReady = 0;
end
endmodule endmodule