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fixed lints in cnt

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This commit is contained in:
Kevin Kim 2023-02-11 20:22:42 -08:00
parent 38087be3b7
commit fb99bdab82
1 changed files with 10 additions and 9 deletions
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19
src/ieu/bmu/cnt.sv
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@ -48,25 +48,26 @@ module cnt #(parameter WIDTH = 32) (
//NOTE: signal widths can be decreased //NOTE: signal widths can be decreased
always_comb begin always_comb begin
//clz input select mux //clz input select mux
case({B,W64}) case({B[4:0],W64})
5'b00000_0: lzcA = A; //clz 6'b00000_0: lzcA = A; //clz
5'b00000_1: lzcA = {A[31:0],{32{1'b1}}}; //clzw 6'b00000_1: lzcA = {A[31:0],{32{1'b1}}}; //clzw
5'b00001_0: lzcA = revA; //ctz 6'b00001_0: lzcA = revA; //ctz
5'b00001_1: lzcA = {revA[31:0],{32{1'b1}}}; //ctzw 6'b00001_1: lzcA = {revA[31:0],{32{1'b1}}}; //ctzw
endcase endcase
//cpop select mux //cpop select mux
case ({B,W64}) case ({B[4:0],W64})
5'b00010_0: popcntA = A; 6'b00010_0: popcntA = A;
5'b00010_1: popcntA = {{32{1'b0}}, A[31:0]}; 6'b00010_1: popcntA = {{32{1'b0}}, A[31:0]};
endcase endcase
end end
end end
else begin else begin
//rv32
assign popcntA = A; assign popcntA = A;
always_comb begin always_comb begin
//clz input slect mux //clz input slect mux
case(B) case(B[4:0])
5'b00000: lzcA = A; 5'b00000: lzcA = A;
5'b00001: lzcA = revA; 5'b00001: lzcA = revA;
endcase endcase