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fix PC checking during InstrPageFault; fix order of S-mode CSR checking; rename peripheral scopes to not be genblk

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bbracker 2021-07-20 17:55:44 -04:00
parent a02694a529
commit f9b6bd91f5
2 changed files with 17 additions and 14 deletions
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19
wally-pipelined/src/uncore/uncore.sv
View File

@ -87,31 +87,32 @@ module uncore (
generate generate
// tightly integrated memory // tightly integrated memory
dtim #(.BASE(`TIM_BASE), .RANGE(`TIM_RANGE)) dtim (.*); dtim #(.BASE(`TIM_BASE), .RANGE(`TIM_RANGE)) dtim (.*);
if (`BOOTTIM_SUPPORTED) if (`BOOTTIM_SUPPORTED) begin : bootdtim
dtim #(.BASE(`BOOTTIM_BASE), .RANGE(`BOOTTIM_RANGE)) bootdtim(.HSELTim(HSELBootTim), .HREADTim(HREADBootTim), .HRESPTim(HRESPBootTim), .HREADYTim(HREADYBootTim), .*); dtim #(.BASE(`BOOTTIM_BASE), .RANGE(`BOOTTIM_RANGE)) bootdtim(.HSELTim(HSELBootTim), .HREADTim(HREADBootTim), .HRESPTim(HRESPBootTim), .HREADYTim(HREADYBootTim), .*);
end
// memory-mapped I/O peripherals // memory-mapped I/O peripherals
if (`CLINT_SUPPORTED == 1) if (`CLINT_SUPPORTED == 1) begin : clint
clint clint(.HADDR(HADDR[15:0]), .MTIME(MTIME_CLINT), .MTIMECMP(MTIMECMP_CLINT), .*); clint clint(.HADDR(HADDR[15:0]), .MTIME(MTIME_CLINT), .MTIMECMP(MTIMECMP_CLINT), .*);
else begin end else begin : clint
assign MTIME_CLINT = 0; assign MTIMECMP_CLINT = 0; assign MTIME_CLINT = 0; assign MTIMECMP_CLINT = 0;
assign TimerIntM = 0; assign SwIntM = 0; assign TimerIntM = 0; assign SwIntM = 0;
end end
if (`PLIC_SUPPORTED == 1) if (`PLIC_SUPPORTED == 1) begin : plic
plic plic(.HADDR(HADDR[27:0]), .*); plic plic(.HADDR(HADDR[27:0]), .*);
else begin end else begin : plic
assign ExtIntM = 0; assign ExtIntM = 0;
end end
if (`GPIO_SUPPORTED == 1) if (`GPIO_SUPPORTED == 1) begin : gpio
gpio gpio(.HADDR(HADDR[7:0]), .*); gpio gpio(.HADDR(HADDR[7:0]), .*);
else begin end else begin : gpio
assign GPIOPinsOut = 0; assign GPIOPinsEn = 0; assign GPIOIntr = 0; assign GPIOPinsOut = 0; assign GPIOPinsEn = 0; assign GPIOIntr = 0;
end end
if (`UART_SUPPORTED == 1) if (`UART_SUPPORTED == 1) begin : uart
uart uart(.HADDR(HADDR[2:0]), .TXRDYb(), .RXRDYb(), .INTR(UARTIntr), .SIN(UARTSin), .SOUT(UARTSout), uart uart(.HADDR(HADDR[2:0]), .TXRDYb(), .RXRDYb(), .INTR(UARTIntr), .SIN(UARTSin), .SOUT(UARTSout),
.DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1), .DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1),
.RTSb(), .DTRb(), .OUT1b(), .OUT2b(), .*); .RTSb(), .DTRb(), .OUT1b(), .OUT2b(), .*);
else begin end else begin : uart
assign UARTSout = 0; assign UARTIntr = 0; assign UARTSout = 0; assign UARTIntr = 0;
end end
endgenerate endgenerate

12
wally-pipelined/testbench/testbench-linux.sv
View File

@ -27,7 +27,7 @@
module testbench(); module testbench();
parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*2790000; // # of instructions at which to turn on waves in graphical sim parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*3160000; // # of instructions at which to turn on waves in graphical sim
parameter stopICount = `BUSYBEAR*143898 + `BUILDROOT*0000000; // # instructions at which to halt sim completely (set to 0 to let it run as far as it can) parameter stopICount = `BUSYBEAR*143898 + `BUILDROOT*0000000; // # instructions at which to halt sim completely (set to 0 to let it run as far as it can)
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////
@ -140,7 +140,7 @@ module testbench();
end end
// initial loading of memories // initial loading of memories
initial begin initial begin
$readmemh({`LINUX_TEST_VECTORS,"bootmem.txt"}, dut.uncore.bootdtim.RAM, 'h1000 >> 3); $readmemh({`LINUX_TEST_VECTORS,"bootmem.txt"}, dut.uncore.bootdtim.bootdtim.RAM, 'h1000 >> 3);
$readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM); $readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM);
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory); $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory);
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory); $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory);
@ -260,7 +260,7 @@ module testbench();
// Check if PCD is going to be flushed due to a branch or jump // Check if PCD is going to be flushed due to a branch or jump
if (`BPRED_ENABLED) begin if (`BPRED_ENABLED) begin
PCDwrong = dut.hart.hzu.FlushD || (PCtextE.substr(0,3) == "mret"); //Old version: dut.hart.ifu.bpred.bpred.BPPredWrongE; <-- This old version failed to account for MRET. PCDwrong = dut.hart.hzu.FlushD || (PCtextE.substr(0,3) == "mret") || dut.hart.priv.InstrPageFaultF || dut.hart.priv.InstrPageFaultD || dut.hart.priv.InstrPageFaultE || dut.hart.priv.InstrPageFaultM;
end end
// Check PCD, InstrD // Check PCD, InstrD
@ -283,10 +283,10 @@ module testbench();
scan_file_memR = $fscanf(data_file_memR, "%x\n", readAdrExpected); scan_file_memR = $fscanf(data_file_memR, "%x\n", readAdrExpected);
scan_file_memR = $fscanf(data_file_memR, "%x\n", readDataExpected); scan_file_memR = $fscanf(data_file_memR, "%x\n", readDataExpected);
// Next force a timer interrupt (*** this may later need generalizing) // Next force a timer interrupt (*** this may later need generalizing)
force dut.uncore.genblk1.clint.MTIME = dut.uncore.genblk1.clint.MTIMECMP + 1; force dut.uncore.clint.clint.MTIME = dut.uncore.clint.clint.MTIMECMP + 1;
while (clk != 0) #1; while (clk != 0) #1;
while (clk != 1) #1; while (clk != 1) #1;
release dut.uncore.genblk1.clint.MTIME; release dut.uncore.clint.clint.MTIME;
end end
end end
end end
@ -526,6 +526,7 @@ module testbench();
string MTVALstring = "MTVAL"; string MTVALstring = "MTVAL";
string SEPCstring = "SEPC"; string SEPCstring = "SEPC";
string SCAUSEstring = "SCAUSE"; string SCAUSEstring = "SCAUSE";
string STVALstring = "STVAL";
string SSTATUSstring = "SSTATUS"; string SSTATUSstring = "SSTATUS";
logic [63:0] expectedCSR; logic [63:0] expectedCSR;
@ -556,6 +557,7 @@ module testbench();
if (``CSR``name == MTVALstring) #3; \ if (``CSR``name == MTVALstring) #3; \
if (``CSR``name == SEPCstring) #1; \ if (``CSR``name == SEPCstring) #1; \
if (``CSR``name == SCAUSEstring) #2; \ if (``CSR``name == SCAUSEstring) #2; \
if (``CSR``name == STVALstring) #3; \
if (``CSR``name == SSTATUSstring) #3; \ if (``CSR``name == SSTATUSstring) #3; \
scan_file_csr = $fscanf(data_file_csr, "%s\n", expectedCSRname); \ scan_file_csr = $fscanf(data_file_csr, "%s\n", expectedCSRname); \
scan_file_csr = $fscanf(data_file_csr, "%x\n", expectedCSR); \ scan_file_csr = $fscanf(data_file_csr, "%x\n", expectedCSR); \