Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Modify register before fpdivsqrt to be synthesizable for FPGAs and better in tune for ASIC clocking

Browse Source
This commit is contained in:
James E. Stine 2021-10-22 13:41:50 -05:00
parent 7c7c0f538a
commit f6e8e45901
3 changed files with 184 additions and 91 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
wally-pipelined/src/fpu/fpdiv_pipe.sv
View File

@ -42,6 +42,7 @@ module fpdiv_pipe (
output logic done, output logic done,
output logic FDivBusyE, output logic FDivBusyE,
output logic load_preload,
output logic [63:0] AS_Result, output logic [63:0] AS_Result,
output logic [4:0] Flags); output logic [4:0] Flags);
@ -137,18 +138,18 @@ module fpdiv_pipe (
.sel_muxa, .sel_muxb, .sel_muxr, .reset, .clk, .sel_muxa, .sel_muxb, .sel_muxr, .reset, .clk,
.load_rega, .load_regb, .load_regc, .load_regd, .load_rega, .load_regb, .load_regc, .load_regd,
.load_regr, .load_regs, .load_regp, .load_regr, .load_regs, .load_regp,
.P(P1), .op_type(op_type1), .exp_odd(exp_odd1)); .P(P), .op_type(op_type1), .exp_odd(exp_odd1));
// FSM : control divider // FSM : control divider
fsm_fpdiv_pipe control (.clk, .reset, .start(start), .op_type(op_type1), .P(P1), fsm_fpdiv_pipe control (.clk, .reset, .start(start), .op_type(op_type1), .P(P),
.done, .load_rega, .load_regb, .load_regc, .load_regd, .done, .load_rega, .load_regb, .load_regc, .load_regd,
.load_regr, .load_regs, .load_regp, .load_regr, .load_regs, .load_regp, .load_preload,
.sel_muxa, .sel_muxb, .sel_muxr, .divBusy(FDivBusyE)); .sel_muxa, .sel_muxb, .sel_muxr, .divBusy(FDivBusyE));
// Round the mantissa to a 52-bit value, with the leading one // Round the mantissa to a 52-bit value, with the leading one
// removed. The rounding units also handles special cases and // removed. The rounding units also handles special cases and
// set the exception flags. // set the exception flags.
rounder_div round1 (.rm, .P(P1), .OvEn(1'b0), .UnEn(1'b0), .exp_diff(expF1), rounder_div round1 (.rm, .P(P), .OvEn(1'b0), .UnEn(1'b0), .exp_diff(expF1),
.sel_inv(sel_inv1), .Invalid(Invalid1), .SignR(signResult1), .sel_inv(sel_inv1), .Invalid(Invalid1), .SignR(signResult1),
.Float1(op1), .Float2(op2), .Float1(op1), .Float2(op2),
.XNaNQ, .YNaNQ, .XZeroQ, .YZeroQ, .XNaNQ, .YNaNQ, .XZeroQ, .YZeroQ,

28
wally-pipelined/src/fpu/fpu.sv
View File

@ -103,7 +103,8 @@ module fpu (
logic XExpMaxE; // is the exponent all ones (max value) logic XExpMaxE; // is the exponent all ones (max value)
logic XNormE; // is normal logic XNormE; // is normal
logic FmtQ; logic FmtQ;
logic FDivStartQ; logic FDivStartQ;
logic FOpCtrlQ;
// result and flag signals // result and flag signals
logic [63:0] FDivResM, FDivResW; // divide/squareroot result logic [63:0] FDivResM, FDivResW; // divide/squareroot result
@ -128,6 +129,7 @@ module fpu (
logic FDivSqrtDoneE; // is divide done logic FDivSqrtDoneE; // is divide done
logic [63:0] DivInput1E, DivInput2E; // inputs to divide/squareroot unit logic [63:0] DivInput1E, DivInput2E; // inputs to divide/squareroot unit
logic FDivClk; // clock for divide/squareroot unit logic FDivClk; // clock for divide/squareroot unit
logic load_preload; // enable for FF on fpdivsqrt
logic [63:0] AlignedSrcAE; // align SrcA to the floating point format logic [63:0] AlignedSrcAE; // align SrcA to the floating point format
// DECODE STAGE // DECODE STAGE
@ -194,19 +196,19 @@ module fpu (
.FMAFlgM, .FMAResM); .FMAFlgM, .FMAResM);
// fpdivsqrt using Goldschmidt's iteration // fpdivsqrt using Goldschmidt's iteration
floprc #(64) reg_input1 (.d({XSgnE, XExpE, XManE[51:0]}), .q(DivInput1E), flopenrc #(64) reg_input1 (.d({XSgnE, XExpE, XManE[51:0]}), .q(DivInput1E),
.clear(FDivSqrtDoneE), .clear(FDivSqrtDoneE), .en(load_preload),
.reset(reset), .clk(FDivBusyE)); .reset(reset), .clk(clk));
floprc #(64) reg_input2 (.d({YSgnE, YExpE, YManE[51:0]}), .q(DivInput2E), flopenrc #(64) reg_input2 (.d({YSgnE, YExpE, YManE[51:0]}), .q(DivInput2E),
.clear(FDivSqrtDoneE), .clear(FDivSqrtDoneE), .en(load_preload),
.reset(reset), .clk(FDivBusyE)); .reset(reset), .clk(clk));
floprc #(7) reg_input3 (.d({XNaNE, YNaNE, XInfE, YInfE, XZeroE, YZeroE, FmtE}), flopenrc #(8) reg_input3 (.d({XNaNE, YNaNE, XInfE, YInfE, XZeroE, YZeroE, FmtE, FOpCtrlE[0]}),
.q({XNaNQ, YNaNQ, XInfQ, YInfQ, XZeroQ, YZeroQ, FmtQ}), .q({XNaNQ, YNaNQ, XInfQ, YInfQ, XZeroQ, YZeroQ, FmtQ, FOpCtrlQ}),
.clear(FDivSqrtDoneE), .clear(FDivSqrtDoneE), .en(load_preload),
.reset(reset), .clk(FDivBusyE)); .reset(reset), .clk(clk));
fpdiv_pipe fdivsqrt (.op1(DivInput1E), .op2(DivInput2E), .rm(FrmE[1:0]), .op_type(FOpCtrlE[0]), fpdiv_pipe fdivsqrt (.op1(DivInput1E), .op2(DivInput2E), .rm(FrmE[1:0]), .op_type(FOpCtrlQ),
.reset, .clk(clk), .start(FDivStartE), .P(~FmtQ), .OvEn(1'b1), .UnEn(1'b1), .reset, .clk(clk), .start(FDivStartE), .P(~FmtQ), .OvEn(1'b1), .UnEn(1'b1),
.XNaNQ, .YNaNQ, .XInfQ, .YInfQ, .XZeroQ, .YZeroQ, .XNaNQ, .YNaNQ, .XInfQ, .YInfQ, .XZeroQ, .YZeroQ, .load_preload,
.FDivBusyE, .done(FDivSqrtDoneE), .AS_Result(FDivResM), .Flags(FDivFlgM)); .FDivBusyE, .done(FDivSqrtDoneE), .AS_Result(FDivResM), .Flags(FDivFlgM));
// convert from signle to double and vice versa // convert from signle to double and vice versa

238
wally-pipelined/src/fpu/fsm_fpdiv_pipe.sv
View File

@ -28,7 +28,8 @@ module fsm_fpdiv_pipe (
input logic start, input logic start,
input logic op_type, input logic op_type,
input logic P, input logic P,
output logic done, output logic done,
output logic load_preload,
output logic load_rega, output logic load_rega,
output logic load_regb, output logic load_regb,
output logic load_regc, output logic load_regc,
@ -52,7 +53,7 @@ module fsm_fpdiv_pipe (
S30, S31, S32, S33, S34, S35, S36, S37, S38, S39, S30, S31, S32, S33, S34, S35, S36, S37, S38, S39,
S40, S41, S42, S43, S44, S45, S46, S47, S48, S49, S40, S41, S42, S43, S44, S45, S46, S47, S48, S49,
S50, S51, S52, S53, S54, S55, S56, S57, S58, S59, S50, S51, S52, S53, S54, S55, S56, S57, S58, S59,
S60, S61, S62, S63, S64, S65} statetype; S60, S61, S62, S63, S64, S65, S66} statetype;
statetype current_state, next_state; statetype current_state, next_state;
@ -73,6 +74,7 @@ module fsm_fpdiv_pipe (
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b0; divBusy = 1'b0;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -89,6 +91,7 @@ module fsm_fpdiv_pipe (
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b1;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -99,15 +102,33 @@ module fsm_fpdiv_pipe (
sel_muxa = 3'b000; sel_muxa = 3'b000;
sel_muxb = 3'b000; sel_muxb = 3'b000;
sel_muxr = 1'b0; sel_muxr = 1'b0;
next_state = S65; next_state = S66;
end end
end end // case: S0
S66:
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
load_regd = 1'b0;
load_regr = 1'b0;
load_regs = 1'b0;
load_regp = 1'b0;
sel_muxa = 3'b000;
sel_muxb = 3'b000;
sel_muxr = 1'b0;
next_state = S65;
end // if (start==1'b0)
S65: S65:
begin begin
if (op_type==1'b0 && P==1'b0) if (op_type==1'b0 && P==1'b0)
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b1; load_rega = 1'b1;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b1; load_regc = 1'b1;
@ -123,7 +144,8 @@ module fsm_fpdiv_pipe (
else if (op_type==1'b0 && P==1'b1) else if (op_type==1'b0 && P==1'b1)
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b1; load_rega = 1'b1;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b1; load_regc = 1'b1;
@ -139,7 +161,8 @@ module fsm_fpdiv_pipe (
else if (op_type==1'b1 && P==1'b0) else if (op_type==1'b1 && P==1'b0)
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -155,7 +178,8 @@ module fsm_fpdiv_pipe (
else if (op_type==1'b1 && P==1'b1) else if (op_type==1'b1 && P==1'b1)
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -171,7 +195,8 @@ module fsm_fpdiv_pipe (
else else
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b0; divBusy = 1'b0;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -189,7 +214,8 @@ module fsm_fpdiv_pipe (
S1: S1:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b1; load_regb = 1'b1;
load_regc = 1'b0; load_regc = 1'b0;
@ -205,7 +231,8 @@ module fsm_fpdiv_pipe (
S2: // iteration 1 S2: // iteration 1
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b1; load_rega = 1'b1;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b1; load_regc = 1'b1;
@ -221,7 +248,8 @@ module fsm_fpdiv_pipe (
S3: S3:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b1; load_regb = 1'b1;
load_regc = 1'b0; load_regc = 1'b0;
@ -237,7 +265,8 @@ module fsm_fpdiv_pipe (
S4: // iteration 2 S4: // iteration 2
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b1; load_rega = 1'b1;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b1; load_regc = 1'b1;
@ -253,7 +282,8 @@ module fsm_fpdiv_pipe (
S5: S5:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b1; load_regb = 1'b1;
load_regc = 1'b0; load_regc = 1'b0;
@ -269,7 +299,8 @@ module fsm_fpdiv_pipe (
S6: // iteration 3 S6: // iteration 3
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b1; load_rega = 1'b1;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b1; load_regc = 1'b1;
@ -285,7 +316,8 @@ module fsm_fpdiv_pipe (
S7: S7:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b1; load_regb = 1'b1;
load_regc = 1'b0; load_regc = 1'b0;
@ -301,7 +333,8 @@ module fsm_fpdiv_pipe (
S8: S8:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -317,7 +350,8 @@ module fsm_fpdiv_pipe (
S9: // q,qm,qp S9: // q,qm,qp
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -333,7 +367,8 @@ module fsm_fpdiv_pipe (
S10: // rem S10: // rem
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -349,7 +384,8 @@ module fsm_fpdiv_pipe (
S11: S11:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -365,7 +401,8 @@ module fsm_fpdiv_pipe (
S12: S12:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -381,7 +418,8 @@ module fsm_fpdiv_pipe (
S13: S13:
begin begin
done = 1'b1; done = 1'b1;
divBusy = 1'b0; divBusy = 1'b0;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -397,7 +435,8 @@ module fsm_fpdiv_pipe (
S14: S14:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b0; divBusy = 1'b0;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -414,7 +453,8 @@ module fsm_fpdiv_pipe (
S15: S15:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -430,7 +470,8 @@ module fsm_fpdiv_pipe (
S16: S16:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b1; load_rega = 1'b1;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b1; load_regc = 1'b1;
@ -446,7 +487,8 @@ module fsm_fpdiv_pipe (
S17: S17:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b1; load_regb = 1'b1;
load_regc = 1'b0; load_regc = 1'b0;
@ -462,7 +504,8 @@ module fsm_fpdiv_pipe (
S18: // iteration 1 S18: // iteration 1
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -478,7 +521,8 @@ module fsm_fpdiv_pipe (
S19: // iteration 1 S19: // iteration 1
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -494,7 +538,8 @@ module fsm_fpdiv_pipe (
S20: S20:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b1; load_rega = 1'b1;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b1; load_regc = 1'b1;
@ -510,7 +555,8 @@ module fsm_fpdiv_pipe (
S21: S21:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b1; load_regb = 1'b1;
load_regc = 1'b0; load_regc = 1'b0;
@ -526,7 +572,8 @@ module fsm_fpdiv_pipe (
S22: // iteration 2 S22: // iteration 2
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -542,7 +589,8 @@ module fsm_fpdiv_pipe (
S23: S23:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -558,7 +606,8 @@ module fsm_fpdiv_pipe (
S24: S24:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b1; load_rega = 1'b1;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b1; load_regc = 1'b1;
@ -574,7 +623,8 @@ module fsm_fpdiv_pipe (
S25: S25:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b1; load_regb = 1'b1;
load_regc = 1'b0; load_regc = 1'b0;
@ -590,7 +640,8 @@ module fsm_fpdiv_pipe (
S26: // iteration 3 S26: // iteration 3
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -606,7 +657,8 @@ module fsm_fpdiv_pipe (
S27: S27:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -622,7 +674,8 @@ module fsm_fpdiv_pipe (
S28: S28:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b1; load_rega = 1'b1;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b1; load_regc = 1'b1;
@ -638,7 +691,8 @@ module fsm_fpdiv_pipe (
S29: S29:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b1; load_regb = 1'b1;
load_regc = 1'b0; load_regc = 1'b0;
@ -654,7 +708,8 @@ module fsm_fpdiv_pipe (
S30: // q,qm,qp S30: // q,qm,qp
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -670,7 +725,8 @@ module fsm_fpdiv_pipe (
S31: // rem S31: // rem
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -686,7 +742,8 @@ module fsm_fpdiv_pipe (
S32: S32:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -702,7 +759,8 @@ module fsm_fpdiv_pipe (
S33: S33:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -718,7 +776,8 @@ module fsm_fpdiv_pipe (
S34: // done S34: // done
begin begin
done = 1'b1; done = 1'b1;
divBusy = 1'b0; divBusy = 1'b0;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -734,7 +793,8 @@ module fsm_fpdiv_pipe (
S35: S35:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b0; divBusy = 1'b0;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -751,7 +811,8 @@ module fsm_fpdiv_pipe (
S36: S36:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b1; load_regb = 1'b1;
load_regc = 1'b0; load_regc = 1'b0;
@ -767,7 +828,8 @@ module fsm_fpdiv_pipe (
S37: // iteration 1 S37: // iteration 1
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b1; load_rega = 1'b1;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b1; load_regc = 1'b1;
@ -783,7 +845,8 @@ module fsm_fpdiv_pipe (
S38: S38:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b1; load_regb = 1'b1;
load_regc = 1'b0; load_regc = 1'b0;
@ -799,7 +862,8 @@ module fsm_fpdiv_pipe (
S39: // iteration 2 S39: // iteration 2
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b1; load_rega = 1'b1;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b1; load_regc = 1'b1;
@ -815,7 +879,8 @@ module fsm_fpdiv_pipe (
S40: S40:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b1; load_regb = 1'b1;
load_regc = 1'b0; load_regc = 1'b0;
@ -831,7 +896,8 @@ module fsm_fpdiv_pipe (
S41: S41:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -847,7 +913,8 @@ module fsm_fpdiv_pipe (
S42: // q,qm,qp S42: // q,qm,qp
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -863,7 +930,8 @@ module fsm_fpdiv_pipe (
S43: // rem S43: // rem
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -879,7 +947,8 @@ module fsm_fpdiv_pipe (
S44: S44:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -895,7 +964,8 @@ module fsm_fpdiv_pipe (
S45: S45:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -911,7 +981,8 @@ module fsm_fpdiv_pipe (
S46: // done S46: // done
begin begin
done = 1'b1; done = 1'b1;
divBusy = 1'b0; divBusy = 1'b0;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -927,7 +998,8 @@ module fsm_fpdiv_pipe (
S47: S47:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b0; divBusy = 1'b0;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -944,7 +1016,8 @@ module fsm_fpdiv_pipe (
S48: S48:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -960,7 +1033,8 @@ module fsm_fpdiv_pipe (
S49: S49:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b1; load_rega = 1'b1;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b1; load_regc = 1'b1;
@ -976,7 +1050,8 @@ module fsm_fpdiv_pipe (
S50: S50:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b1; load_regb = 1'b1;
load_regc = 1'b0; load_regc = 1'b0;
@ -992,7 +1067,8 @@ module fsm_fpdiv_pipe (
S51: // iteration 1 S51: // iteration 1
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -1008,7 +1084,8 @@ module fsm_fpdiv_pipe (
S52: // iteration 1 S52: // iteration 1
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -1024,7 +1101,8 @@ module fsm_fpdiv_pipe (
S53: S53:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b1; load_rega = 1'b1;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b1; load_regc = 1'b1;
@ -1040,7 +1118,8 @@ module fsm_fpdiv_pipe (
S54: S54:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b1; load_regb = 1'b1;
load_regc = 1'b0; load_regc = 1'b0;
@ -1056,7 +1135,8 @@ module fsm_fpdiv_pipe (
S55: // iteration 2 S55: // iteration 2
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -1072,7 +1152,8 @@ module fsm_fpdiv_pipe (
S56: S56:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -1088,7 +1169,8 @@ module fsm_fpdiv_pipe (
S57: S57:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b1; load_rega = 1'b1;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b1; load_regc = 1'b1;
@ -1104,7 +1186,8 @@ module fsm_fpdiv_pipe (
S58: S58:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b1; load_regb = 1'b1;
load_regc = 1'b0; load_regc = 1'b0;
@ -1120,7 +1203,8 @@ module fsm_fpdiv_pipe (
S59: // q,qm,qp S59: // q,qm,qp
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -1136,7 +1220,8 @@ module fsm_fpdiv_pipe (
S60: // rem S60: // rem
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -1152,7 +1237,8 @@ module fsm_fpdiv_pipe (
S61: S61:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -1168,7 +1254,8 @@ module fsm_fpdiv_pipe (
S62: S62:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b1; divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -1184,7 +1271,8 @@ module fsm_fpdiv_pipe (
S63: // done S63: // done
begin begin
done = 1'b1; done = 1'b1;
divBusy = 1'b0; divBusy = 1'b0;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -1200,7 +1288,8 @@ module fsm_fpdiv_pipe (
S64: S64:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b0; divBusy = 1'b0;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;
@ -1216,7 +1305,8 @@ module fsm_fpdiv_pipe (
default: default:
begin begin
done = 1'b0; done = 1'b0;
divBusy = 1'b0; divBusy = 1'b0;
load_preload = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;