forked from Github_Repos/cvw
		
	fdivsqrt post processing simplification
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				@ -101,7 +101,7 @@ module fdivsqrtpostproc(
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  if (`IDIV_ON_FPU) begin // Int supported
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					  if (`IDIV_ON_FPU) begin // Int supported
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    logic [`DIVBLEN:0] NormShiftM;
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					    logic [`DIVBLEN:0] NormShiftM;
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    logic [`DIVb+3:0] IntQuotM, IntRemM, NormRemM, NormRemDM, NormQuotM;
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					    logic [`DIVb+3:0] IntQuotM, NormRemM, NormRemDM, NormQuotM;
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    assign W = $signed(Sum) >>> `LOGR;
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					    assign W = $signed(Sum) >>> `LOGR;
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    assign DM = {4'b0001, D};
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					    assign DM = {4'b0001, D};
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@ -121,19 +121,13 @@ module fdivsqrtpostproc(
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        else        SpecialFPIntDivResultM = '0;
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					        else        SpecialFPIntDivResultM = '0;
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      end else begin
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					      end else begin
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        logic [`DIVb+3:0] PreIntQuotM;
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					        logic [`DIVb+3:0] PreIntQuotM;
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        if (WZeroM) begin
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					        PreIntQuotM = {3'b000, PreQmM};
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          PreIntQuotM = weq0M ? {3'b000, FirstU} :  {3'b000, FirstUM};
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          IntRemM  = '0;
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        end else begin 
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          PreIntQuotM = {3'b000, PreQmM};
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          IntRemM  = NormRemM;
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        end 
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        // flip sign if necessary
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					        // flip sign if necessary
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        if (NegQuotM) IntQuotM = -PreIntQuotM;
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					        if (NegQuotM) IntQuotM = -PreIntQuotM;
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        else          IntQuotM =  PreIntQuotM;
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					        else          IntQuotM =  PreIntQuotM;
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        if (RemOpM) begin
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					        if (RemOpM) begin
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          NormShiftM = ALTBM ? 0 : (mM + (`DIVBLEN+1)'(`DIVa)); // no postshift if forwarding input A to remainder
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					          NormShiftM = ALTBM ? 0 : (mM + (`DIVBLEN+1)'(`DIVa)); // no postshift if forwarding input A to remainder
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          PreResultM = IntRemM;
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					          PreResultM = NormRemM;
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        end else begin
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					        end else begin
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          NormShiftM = ((`DIVBLEN+1)'(`DIVb) - (nM * (`DIVBLEN+1)'(`LOGR)));
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					          NormShiftM = ((`DIVBLEN+1)'(`DIVb) - (nM * (`DIVBLEN+1)'(`LOGR)));
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          PreResultM = IntQuotM;
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					          PreResultM = IntQuotM;
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