forked from Github_Repos/cvw
		
	removed unnecessary signal indices
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				@ -32,7 +32,7 @@
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module cnt #(parameter WIDTH = 32) (
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  input  logic [WIDTH-1:0] A, RevA,    // Operands
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  input  logic [4:0] B,                // Last 5 bits of immediate
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  input  logic [1:0] B,                // Last 2 bits of immediate
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  input  logic W64,                    // Indicates word operation
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  output logic [WIDTH-1:0] CntResult   // count result
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);
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@ -42,7 +42,7 @@ module zbb #(parameter WIDTH=32) (
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  logic [WIDTH-1:0] ByteResult;          // byte results
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  logic [WIDTH-1:0] ExtResult;           // sign/zero extend results
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  cnt #(WIDTH) cnt(.A, .RevA, .B(B[4:0]), .W64, .CntResult);
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  cnt #(WIDTH) cnt(.A, .RevA, .B(B[1:0]), .W64, .CntResult);
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  byteUnit #(WIDTH) bu(.A, .ByteSelect(B[0]), .ByteResult);
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  ext #(WIDTH) ext(.A, .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult);
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