forked from Github_Repos/cvw
uncore cleanup
This commit is contained in:
David Harris
parent
1ec42b9d50
commit
f16267ddbc
@ -1,55 +0,0 @@
|
||||
SD Flash interface
|
||||
|
||||
regsiter map:
|
||||
1. clock divider
|
||||
2. address
|
||||
3. data register
|
||||
4. command register
|
||||
5. size register
|
||||
Number of bytes to read or write.
|
||||
6. status register
|
||||
1. bits 11 to 0: bytes currently in the buffer
|
||||
2. bits 12 to 29: reservered
|
||||
3. bit 30: fault
|
||||
4. bit 31: busy
|
||||
5. bits XLEN-1 to 32: reservered
|
||||
|
||||
|
||||
|
||||
non dma read operation
|
||||
1. write the address regsiter
|
||||
2. write the command register to read
|
||||
3. wait for interrupt or pool on status
|
||||
4. Check status for fault and number of bytes.
|
||||
5. read the data register for 512 bytes. (64 ld, or 128 lw)
|
||||
|
||||
|
||||
non dma write operation
|
||||
1. write address register
|
||||
2. write data register for 512 bytes. (64 sd, or 128 sw)
|
||||
3. write command register to write data to flash
|
||||
4. wait for interrupt or pool on status
|
||||
5. check status for fault and number of bytes written.
|
||||
|
||||
implement dma transfers later
|
||||
|
||||
|
||||
interrupts
|
||||
1. operation done
|
||||
2. bus error (more of an exception)
|
||||
Occurs if attempting to do an operation while the flash controller is busy.
|
||||
ie. if status[31] is set generate an interrupt
|
||||
This is tricky in a multiprocessor environment.
|
||||
|
||||
|
||||
|
||||
|
||||
tasks
|
||||
1. [-] Remove all AFRL identifiers
|
||||
2. [X] get the existing sdc compiled on wally.
|
||||
1. [X] use wally primatives over tcore's
|
||||
3. build abhlite interface with the above registers and necessary fsm.
|
||||
1. [ ] The sd card reader uses a 4 bit data interface. We can change this to be something
|
||||
more pratical.
|
||||
4. write test programs
|
||||
5. [X] Convert VHDL to system verilog
|
||||
@ -3,13 +3,13 @@
|
||||
//
|
||||
// Written: Richard Davis
|
||||
// Modified: Ross Thompson
|
||||
// Converted to system verilog.
|
||||
// Converted to SystemVerilog.
|
||||
//
|
||||
// Purpose: basic up counter
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
/ SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
|
||||
@ -48,17 +48,18 @@ module uncore (
|
||||
output logic HREADY, HRESP,
|
||||
output logic HSELEXT,
|
||||
// peripheral pins
|
||||
output logic MTimerInt, MSwInt, MExtInt, SExtInt,
|
||||
input logic [31:0] GPIOPinsIn,
|
||||
output logic [31:0] GPIOPinsOut, GPIOPinsEn,
|
||||
input logic UARTSin,
|
||||
output logic UARTSout,
|
||||
output logic SDCCmdOut,
|
||||
output logic SDCCmdOE,
|
||||
input logic SDCCmdIn,
|
||||
input logic [3:0] SDCDatIn,
|
||||
output logic SDCCLK,
|
||||
output logic [63:0] MTIME_CLINT
|
||||
output logic MTimerInt, MSwInt, // Timer and software interrupts from CLINT
|
||||
output logic MExtInt, SExtInt, // External interrupts from PLIC
|
||||
output logic [63:0] MTIME_CLINT, // MTIME, from CLINT
|
||||
input logic [31:0] GPIOPinsIn, // GPIO pin input value
|
||||
output logic [31:0] GPIOPinsOut, GPIOPinsEn, // GPIO pin output value and enable
|
||||
input logic UARTSin, // UART serial input
|
||||
output logic UARTSout, // UART serial output
|
||||
output logic SDCCmdOut, // SD Card command output
|
||||
output logic SDCCmdOE, // SD Card command output enable
|
||||
input logic SDCCmdIn, // SD Card command input
|
||||
input logic [3:0] SDCDatIn, // SD Card data input
|
||||
output logic SDCCLK // SD Card clock
|
||||
);
|
||||
|
||||
logic [`XLEN-1:0] HREADRam, HREADSDC;
|
||||
@ -92,54 +93,42 @@ module uncore (
|
||||
assign {HSELDTIM, HSELIROM, HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[10:1];
|
||||
|
||||
// AHB -> APB bridge
|
||||
ahbapbbridge #(4) ahbapbbridge
|
||||
(.HCLK, .HRESETn, .HSEL({HSELUART, HSELPLIC, HSELCLINT, HSELGPIO}), .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HTRANS, .HREADY,
|
||||
ahbapbbridge #(4) ahbapbbridge (
|
||||
.HCLK, .HRESETn, .HSEL({HSELUART, HSELPLIC, HSELCLINT, HSELGPIO}), .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HTRANS, .HREADY,
|
||||
.HRDATA(HREADBRIDGE), .HRESP(HRESPBRIDGE), .HREADYOUT(HREADYBRIDGE),
|
||||
.PCLK, .PRESETn, .PSEL, .PWRITE, .PENABLE, .PADDR, .PWDATA, .PSTRB, .PREADY, .PRDATA);
|
||||
assign HSELBRIDGE = HSELGPIO | HSELCLINT | HSELPLIC | HSELUART; // if any of the bridge signals are selected
|
||||
|
||||
// on-chip RAM
|
||||
if (`UNCORE_RAM_SUPPORTED) begin : ram
|
||||
ram_ahb #(
|
||||
.BASE(`UNCORE_RAM_BASE), .RANGE(`UNCORE_RAM_RANGE)) ram (
|
||||
.HCLK, .HRESETn,
|
||||
.HSELRam, .HADDR,
|
||||
.HWRITE, .HREADY,
|
||||
.HTRANS, .HWDATA, .HWSTRB, .HREADRam,
|
||||
.HRESPRam, .HREADYRam);
|
||||
ram_ahb #(.BASE(`UNCORE_RAM_BASE), .RANGE(`UNCORE_RAM_RANGE)) ram (
|
||||
.HCLK, .HRESETn, .HSELRam, .HADDR, .HWRITE, .HREADY,
|
||||
.HTRANS, .HWDATA, .HWSTRB, .HREADRam, .HRESPRam, .HREADYRam);
|
||||
end
|
||||
|
||||
if (`BOOTROM_SUPPORTED) begin : bootrom
|
||||
rom_ahb #(.BASE(`BOOTROM_BASE), .RANGE(`BOOTROM_RANGE))
|
||||
bootrom(
|
||||
.HCLK, .HRESETn,
|
||||
.HSELRom(HSELBootRom), .HADDR,
|
||||
.HREADY, .HTRANS,
|
||||
bootrom(.HCLK, .HRESETn, .HSELRom(HSELBootRom), .HADDR, .HREADY, .HTRANS,
|
||||
.HREADRom(HREADBootRom), .HRESPRom(HRESPBootRom), .HREADYRom(HREADYBootRom));
|
||||
end
|
||||
|
||||
// memory-mapped I/O peripherals
|
||||
if (`CLINT_SUPPORTED == 1) begin : clint
|
||||
clint_apb clint(
|
||||
.PCLK, .PRESETn, .PSEL(PSEL[1]), .PADDR(PADDR[15:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE,
|
||||
.PRDATA(PRDATA[1]), .PREADY(PREADY[1]),
|
||||
.MTIME(MTIME_CLINT),
|
||||
.MTimerInt, .MSwInt);
|
||||
|
||||
clint_apb clint(.PCLK, .PRESETn, .PSEL(PSEL[1]), .PADDR(PADDR[15:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE,
|
||||
.PRDATA(PRDATA[1]), .PREADY(PREADY[1]), .MTIME(MTIME_CLINT), .MTimerInt, .MSwInt);
|
||||
end else begin : clint
|
||||
assign MTIME_CLINT = 0;
|
||||
assign MTimerInt = 0; assign MSwInt = 0;
|
||||
end
|
||||
|
||||
if (`PLIC_SUPPORTED == 1) begin : plic
|
||||
plic_apb plic(
|
||||
.PCLK, .PRESETn, .PSEL(PSEL[2]), .PADDR(PADDR[27:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE,
|
||||
.PRDATA(PRDATA[2]), .PREADY(PREADY[2]),
|
||||
.UARTIntr, .GPIOIntr,
|
||||
.MExtInt, .SExtInt);
|
||||
plic_apb plic(.PCLK, .PRESETn, .PSEL(PSEL[2]), .PADDR(PADDR[27:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE,
|
||||
.PRDATA(PRDATA[2]), .PREADY(PREADY[2]), .UARTIntr, .GPIOIntr, .MExtInt, .SExtInt);
|
||||
end else begin : plic
|
||||
assign MExtInt = 0;
|
||||
assign SExtInt = 0;
|
||||
end
|
||||
|
||||
if (`GPIO_SUPPORTED == 1) begin : gpio
|
||||
gpio_apb gpio(
|
||||
.PCLK, .PRESETn, .PSEL(PSEL[0]), .PADDR(PADDR[7:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE,
|
||||
@ -197,7 +186,9 @@ module uncore (
|
||||
// takes more than 1 cycle to repsond it needs to hold on to the old select until the
|
||||
// device is ready. Hense this register must be selectively enabled by HREADY.
|
||||
// However on reset None must be seleted.
|
||||
flopenl #(11) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions, 11'b1, {HSELDTIMD, HSELIROMD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD, HSELNoneD});
|
||||
flopenl #(11) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions, 11'b1,
|
||||
{HSELDTIMD, HSELIROMD, HSELEXTD, HSELBootRomD, HSELRamD,
|
||||
HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD, HSELNoneD});
|
||||
flopenr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HREADY, HSELBRIDGE, HSELBRIDGED);
|
||||
endmodule
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user