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busybear: remove gpio, start adding 2nd ram

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This commit is contained in:
Noah Boorstin 2021-02-28 06:02:40 +00:00
parent e5e345d161
commit edd5e9106d
2 changed files with 10 additions and 6 deletions
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10
wally-pipelined/config/busybear/wally-config.vh
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@ -62,11 +62,13 @@
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
`define TIMBASE 64'h0000000080000000
`define TIMRANGE 64'h000000000007FFFF
`define TIMRANGE 64'h0000000007FFFFFF
`define BOOTTIMBASE 64'h0000000000000000 //only needs to go from 0x1000 to 0x2FFF, extending to a power of 2
`define BOOTTIMRANGE 64'h0000000000004000
`define CLINTBASE 64'h0000000002000000
`define CLINTRANGE 64'h000000000000FFFF
`define GPIOBASE 64'h0000000010012000
`define GPIORANGE 64'h00000000000000FF
`define CLINTRANGE 64'h000000000000BFFF
//`define GPIOBASE 64'h0000000010012000 // no GPIO in linux for now
//`define GPIORANGE 64'h00000000000000FF
`define UARTBASE 64'h0000000010000000
`define UARTRANGE 64'h0000000000000007
// Bus Interface width

6
wally-pipelined/src/uncore/uncore.sv
View File

@ -59,7 +59,7 @@ module uncore (
logic [`XLEN-1:0] HWDATA;
logic [`XLEN-1:0] HREADTim, HREADCLINT, HREADGPIO, HREADUART;
logic HSELTim, HSELCLINT, HSELGPIO, PreHSELUART, HSELUART;
logic HSELBootTim, HSELTim, HSELCLINT, HSELGPIO, PreHSELUART, HSELUART;
logic HRESPTim, HRESPCLINT, HRESPGPIO, HRESPUART;
logic HREADYTim, HREADYCLINT, HREADYGPIO, HREADYUART;
logic [1:0] MemRW;
@ -69,8 +69,10 @@ module uncore (
// AHB Address decoder
adrdec timdec(HADDR, `TIMBASE, `TIMRANGE, HSELTim);
adrdec boottimdec(HADDR, `BOOTTIMBASE, `BOOTTIMRANGE, HSELBootTim);
adrdec clintdec(HADDR, `CLINTBASE, `CLINTRANGE, HSELCLINT);
adrdec gpiodec(HADDR, `GPIOBASE, `GPIORANGE, HSELGPIO);
//Busybear: for now, leaving out gpio since OVPsim doesn't seem to have it
//adrdec gpiodec(HADDR, `GPIOBASE, `GPIORANGE, HSELGPIO);
adrdec uartdec(HADDR, `UARTBASE, `UARTRANGE, PreHSELUART);
assign HSELUART = PreHSELUART && (HSIZE == 3'b000); // only byte writes to UART are supported