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Removed da page fault from spill logic.

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This commit is contained in:
Ross Thompson 2022-12-30 12:51:56 -06:00
parent 80a135f101
commit ed536dd142
2 changed files with 3 additions and 4 deletions
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4
pipelined/src/ifu/ifu.sv
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@ -128,8 +128,8 @@ module ifu (
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
if(`C_SUPPORTED) begin : SpillSupport if(`C_SUPPORTED) begin : SpillSupport
spillsupport #(`ICACHE) spillsupport(.clk, .reset, .StallF, .Flush(FlushD), .PCF, .PCPlus4F, .PCNextF, .InstrRawF(InstrRawF), spillsupport #(`ICACHE) spillsupport(.clk, .reset, .StallF, .Flush(FlushD), .PCF, .PCPlus4F, .PCNextF, .InstrRawF,
.InstrDAPageFaultF, .IFUCacheBusStallD, .ITLBMissF, .PCNextFSpill, .PCFSpill, .IFUCacheBusStallD, .ITLBMissF, .PCNextFSpill, .PCFSpill,
.SelNextSpillF, .PostSpillInstrRawF, .CompressedF); .SelNextSpillF, .PostSpillInstrRawF, .CompressedF);
end else begin : NoSpillSupport end else begin : NoSpillSupport
assign PCNextFSpill = PCNextF; assign PCNextFSpill = PCNextF;

3
pipelined/src/ifu/spillsupport.sv
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@ -42,7 +42,6 @@ module spillsupport #(parameter CACHE_ENABLED)
input logic [31:0] InstrRawF, input logic [31:0] InstrRawF,
input logic IFUCacheBusStallD, input logic IFUCacheBusStallD,
input logic ITLBMissF, input logic ITLBMissF,
input logic InstrDAPageFaultF,
output logic [`XLEN-1:0] PCNextFSpill, output logic [`XLEN-1:0] PCNextFSpill,
output logic [`XLEN-1:0] PCFSpill, output logic [`XLEN-1:0] PCFSpill,
output logic SelNextSpillF, output logic SelNextSpillF,
@ -68,7 +67,7 @@ module spillsupport #(parameter CACHE_ENABLED)
assign PossibleSpillF = &PCF[$clog2(SPILLTHRESHOLD)+1:1]; assign PossibleSpillF = &PCF[$clog2(SPILLTHRESHOLD)+1:1];
assign SpillF = PossibleSpillF & ~FirstHalfCompressedF & ~IFUCacheBusStallD; assign SpillF = PossibleSpillF & ~FirstHalfCompressedF & ~IFUCacheBusStallD;
assign TakeSpillF = SpillF & ~IFUCacheBusStallD & ~(ITLBMissF | (`HPTW_WRITES_SUPPORTED & InstrDAPageFaultF)); assign TakeSpillF = SpillF & ~ITLBMissF;
always_ff @(posedge clk) always_ff @(posedge clk)
if (reset | Flush) CurrState <= #1 STATE_READY; if (reset | Flush) CurrState <= #1 STATE_READY;