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Missing files related to rv32imc config

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This commit is contained in:
David Harris 2023-01-29 11:40:08 -08:00
parent d1afc2f14a
commit ec675f01a7
2 changed files with 1 additions and 32 deletions
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31
.gitignore vendored
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@ -81,37 +81,6 @@ synthDC/runArchive
synthDC/hdl
/pipelined/regression/power.saif
tests/fp/vectors/*.tv
# Temporary configs produced for synthesis
pipelined/config/rv32e_FPUoff
pipelined/config/rv32e_PMP0
pipelined/config/rv32e_PMP16
pipelined/config/rv32e_noMulDiv
pipelined/config/rv32e_noPriv
pipelined/config/rv32e_orig
pipelined/config/rv32gc_FPUoff
pipelined/config/rv32gc_PMP0
pipelined/config/rv32gc_PMP16
pipelined/config/rv32gc_noMulDiv
pipelined/config/rv32gc_noPriv
pipelined/config/rv32gc_orig
pipelined/config/rv32ic_FPUoff
pipelined/config/rv32ic_PMP0
pipelined/config/rv32ic_PMP16
pipelined/config/rv32ic_noMulDiv
pipelined/config/rv32ic_noPriv
pipelined/config/rv32ic_orig
pipelined/config/rv64gc_FPUoff
pipelined/config/rv64gc_PMP0
pipelined/config/rv64gc_PMP16
pipelined/config/rv64gc_noMulDiv
pipelined/config/rv64gc_noPriv
pipelined/config/rv64gc_orig
pipelined/config/rv64ic_FPUoff
pipelined/config/rv64ic_PMP0
pipelined/config/rv64ic_PMP16
pipelined/config/rv64ic_noMulDiv
pipelined/config/rv64ic_noPriv
pipelined/config/rv64ic_orig
synthDC/Summary.csv
pipelined/srt/exptestgen
pipelined/srt/testgen

2
synthDC/Makefile
View File

@ -45,7 +45,7 @@ default:
@echo "Use wallySynth.py to run a concurrent sweep "
DIRS32 = rv32e rv32gc rv32ic rv32i
DIRS32 = rv32e rv32gc rv32imc rv32i
DIRS64 = rv64i rv64gc
DIRS = $(DIRS32) $(DIRS64)