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added BSelect Signal

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- BSelect [3:0] is a one hot encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction
This commit is contained in:
Kevin Kim 2023-02-17 08:21:55 -08:00
parent 81cb00aaee
commit ec2421ead4
5 changed files with 38 additions and 30 deletions
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18
src/ieu/alu.sv
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@ -33,6 +33,7 @@ module alu #(parameter WIDTH=32) (
input logic [WIDTH-1:0] A, B, // Operands input logic [WIDTH-1:0] A, B, // Operands
input logic [2:0] ALUControl, // With Funct3, indicates operation to perform input logic [2:0] ALUControl, // With Funct3, indicates operation to perform
input logic [2:0] ALUSelect, // ALU mux select signal input logic [2:0] ALUSelect, // ALU mux select signal
input logic [3:0] BSelect, // One-Hot encoding of ZBA_ZBB_ZBC_ZBS instruction
input logic [6:0] Funct7, // Funct7 from execute stage (we only need this for b instructions and should be optimized out later) input logic [6:0] Funct7, // Funct7 from execute stage (we only need this for b instructions and should be optimized out later)
input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect
output logic [WIDTH-1:0] Result, // ALU result output logic [WIDTH-1:0] Result, // ALU result
@ -40,15 +41,18 @@ module alu #(parameter WIDTH=32) (
// CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction.
// FullResult = ALU result before adjusting for a RV64 w-suffix instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction.
logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,ALUResult, ZBCResult; // Intermediate results logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,ALUResult, ZBCResult, CondMaskB; // Intermediate results
logic Carry, Neg; // Flags: carry out, negative logic Carry, Neg; // Flags: carry out, negative
logic LT, LTU; // Less than, Less than unsigned logic LT, LTU; // Less than, Less than unsigned
logic W64; // RV64 W-type instruction logic W64; // RV64 W-type instruction
logic SubArith; // Performing subtraction or arithmetic right shift logic SubArith; // Performing subtraction or arithmetic right shift
logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops
logic Asign, Bsign; // Sign bits of A, B logic Asign, Bsign; // Sign bits of A, B
logic Rotate; logic Rotate;
decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], CondMaskB);
// Extract control signals from ALUControl. // Extract control signals from ALUControl.
assign {W64, SubArith, ALUOp} = ALUControl; assign {W64, SubArith, ALUOp} = ALUControl;

33
src/ieu/bmu/bmuctrl.sv
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@ -36,19 +36,20 @@ module bmuctrl(
input logic StallD, FlushD, // Stall, flush Decode stage input logic StallD, FlushD, // Stall, flush Decode stage
input logic [31:0] InstrD, // Instruction in Decode stage input logic [31:0] InstrD, // Instruction in Decode stage
output logic [2:0] ALUSelectD, // ALU Mux select signal output logic [2:0] ALUSelectD, // ALU Mux select signal
output logic bextD, // Indicates if bit extract instruction
// Execute stage control signals // Execute stage control signals
input logic StallE, FlushE, // Stall, flush Execute stage input logic StallE, FlushE, // Stall, flush Execute stage
output logic [6:0] Funct7E, // Instruction's funct7 field (note: eventually want to get rid of this) output logic [6:0] Funct7E, // Instruction's funct7 field (note: eventually want to get rid of this)
output logic [2:0] ALUSelectE output logic [2:0] ALUSelectE,
output logic [3:0] BSelectE // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding
); );
logic [6:0] OpD; // Opcode in Decode stage logic [6:0] OpD; // Opcode in Decode stage
logic [2:0] Funct3D; // Funct3 field in Decode stage logic [2:0] Funct3D; // Funct3 field in Decode stage
logic [6:0] Funct7D; // Funct7 field in Decode stage logic [6:0] Funct7D; // Funct7 field in Decode stage
logic [4:0] Rs1D; // Rs1 source register in Decode stage logic [4:0] Rs1D; // Rs1 source register in Decode stage
logic [3:0] BSelectD; // Indicates if ZBA_ZBB_ZBC_ZBS instruction decode stage
`define BMUCTRLW 4 `define BMUCTRLW 7
logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals
@ -62,25 +63,25 @@ module bmuctrl(
// Main Instruction Decoder // Main Instruction Decoder
always_comb always_comb
casez({OpD, Funct7D, Funct3D}) casez({OpD, Funct7D, Funct3D})
// ALUSelect_bextD // ALUSelect_zbsD
17'b0010011_010010?_001: BMUControlsD = `BMUCTRLW'b111_0; // bclri 17'b0010011_010010?_001: BMUControlsD = `BMUCTRLW'b111_0001; // bclri
17'b0010011_010010?_101: BMUControlsD = `BMUCTRLW'b101_1; // bexti 17'b0010011_010010?_101: BMUControlsD = `BMUCTRLW'b101_0001; // bexti
17'b0010011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0; // binvi 17'b0010011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0001; // binvi
17'b0010011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0; // bseti 17'b0010011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0001; // bseti
17'b0110011_010010?_001: BMUControlsD = `BMUCTRLW'b111_0; // bclr 17'b0110011_010010?_001: BMUControlsD = `BMUCTRLW'b111_0001; // bclr
17'b0110011_010010?_101: BMUControlsD = `BMUCTRLW'b101_1; // bext 17'b0110011_010010?_101: BMUControlsD = `BMUCTRLW'b101_0001; // bext
17'b0110011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0; // binv 17'b0110011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0001; // binv
17'b0110011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0; // bset 17'b0110011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0001; // bset
17'b0110011_0?00000_?01: BMUControlsD = `BMUCTRLW'b001_0; // sra, srl, sll 17'b0110011_0?00000_?01: BMUControlsD = `BMUCTRLW'b001_0001; // sra, srl, sll
default: BMUControlsD = {Funct3D, {1'b0}};// not B instruction or shift default: BMUControlsD = {Funct3D, {4'b0}}; // not B instruction or shift
endcase endcase
// Unpack Control Signals // Unpack Control Signals
assign {ALUSelectD,bextD} = BMUControlsD; assign {ALUSelectD,BSelectD} = BMUControlsD;
// BMU Execute stage pipieline control register // BMU Execute stage pipieline control register
flopenrc#(10) controlregBMU(clk, reset, FlushE, ~StallE, {Funct7D, ALUSelectD}, {Funct7E, ALUSelectE}); flopenrc#(14) controlregBMU(clk, reset, FlushE, ~StallE, {Funct7D, ALUSelectD, BSelectD}, {Funct7E, ALUSelectE, BSelectE});
endmodule endmodule

9
src/ieu/controller.sv
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@ -56,6 +56,7 @@ module controller(
output logic JumpE, // jump instruction output logic JumpE, // jump instruction
output logic SCE, // Store Conditional instruction output logic SCE, // Store Conditional instruction
output logic BranchSignedE, // Branch comparison operands are signed (if it's a branch) output logic BranchSignedE, // Branch comparison operands are signed (if it's a branch)
output logic [3:0] BSelectE, // One-Hot encoding of if it's ZBA_ZBB_ZBC_ZBS instruction
// Memory stage control signals // Memory stage control signals
input logic StallM, FlushM, // Stall, flush Memory stage input logic StallM, FlushM, // Stall, flush Memory stage
output logic [1:0] MemRWM, // Mem read/write: MemRWM[1] = 1 for read, MemRWM[0] = 1 for write output logic [1:0] MemRWM, // Mem read/write: MemRWM[1] = 1 for read, MemRWM[0] = 1 for write
@ -104,7 +105,7 @@ module controller(
logic InvalidateICacheE, FlushDCacheE;// Invalidate I$, flush D$ logic InvalidateICacheE, FlushDCacheE;// Invalidate I$, flush D$
logic [`CTRLW-1:0] ControlsD; // Main Instruction Decoder control signals logic [`CTRLW-1:0] ControlsD; // Main Instruction Decoder control signals
logic SubArithD; // TRUE for R-type subtracts and sra, slt, sltu logic SubArithD; // TRUE for R-type subtracts and sra, slt, sltu
logic subD, sraD, sltD, sltuD, bextD; // Indicates if is one of these instructions logic subD, sraD, sltD, sltuD; // Indicates if is one of these instructions
logic BranchTakenE; // Branch is taken logic BranchTakenE; // Branch is taken
logic eqE, ltE; // Comparator outputs logic eqE, ltE; // Comparator outputs
logic unused; logic unused;
@ -197,15 +198,15 @@ module controller(
assign sltuD = (Funct3D == 3'b011); assign sltuD = (Funct3D == 3'b011);
assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi
assign sraD = (Funct3D == 3'b101 & Funct7D[5]); assign sraD = (Funct3D == 3'b101 & Funct7D[5]);
assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & bextD)); // TRUE for R-type subtracts and sra, slt, sltu assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & BSelectE[0] & ALUSelectD == 3'b101)); // TRUE for R-type subtracts and sra, slt, sltu, bext
assign ALUControlD = {W64D, SubArithD, ALUOpD}; assign ALUControlD = {W64D, SubArithD, ALUOpD};
if (`ZBS_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags if (`ZBS_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags
bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .bextD, .StallE, .FlushE, .Funct7E, .ALUSelectE); bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .StallE, .FlushE, .Funct7E, .ALUSelectE, BSelectE);
end else begin: bitmanipi end else begin: bitmanipi
assign ALUSelectD = Funct3D; assign ALUSelectD = Funct3D;
assign ALUSelectE = Funct3E; assign ALUSelectE = Funct3E;
assign bextD = 1'b0; assign BSelectE = 4'b000;
assign Funct7E = 7'b0; assign Funct7E = 7'b0;
end end

3
src/ieu/datapath.sv
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@ -18,6 +18,7 @@ module datapath (
input logic [2:0] ALUSelectE, // ALU mux select signal input logic [2:0] ALUSelectE, // ALU mux select signal
input logic JumpE, // Is a jump (j) instruction input logic JumpE, // Is a jump (j) instruction
input logic BranchSignedE, // Branch comparison operands are signed (if it's a branch) input logic BranchSignedE, // Branch comparison operands are signed (if it's a branch)
input logic [3:0] BSelectE, // One hot encoding of ZBA_ZBB_ZBC_ZBS instruction
output logic [1:0] FlagsE, // Comparison flags ({eq, lt}) output logic [1:0] FlagsE, // Comparison flags ({eq, lt})
output logic [`XLEN-1:0] IEUAdrE, // Address computed by ALU output logic [`XLEN-1:0] IEUAdrE, // Address computed by ALU
output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU sources before the mux chooses between them and PCE to put in srcA/B output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU sources before the mux chooses between them and PCE to put in srcA/B
@ -82,7 +83,7 @@ module datapath (
comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE); comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE);
mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE);
mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE); mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE);
alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUSelectE, Funct7E, Funct3E, ALUResultE, IEUAdrE); alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUSelectE, BSelectE, Funct7E, Funct3E, ALUResultE, IEUAdrE);
mux2 #(`XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE); mux2 #(`XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE);
mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE); mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE);

5
src/ieu/ieu.sv
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@ -83,6 +83,7 @@ module ieu (
logic SCE; // Store Conditional instruction logic SCE; // Store Conditional instruction
logic FWriteIntM; // FPU writing to integer register file logic FWriteIntM; // FPU writing to integer register file
logic IntDivW; // Integer divide instruction logic IntDivW; // Integer divide instruction
logic [3:0] BSelectE; // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding
// Forwarding signals // Forwarding signals
logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E; // Source and destination registers logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E; // Source and destination registers
@ -96,7 +97,7 @@ module ieu (
controller c( controller c(
.clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD, .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD,
.IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, .StallE, .FlushE, .FlagsE, .FWriteIntE, .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, .StallE, .FlushE, .FlagsE, .FWriteIntE,
.PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE, .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .BSelectE, .MemReadE, .CSRReadE,
.Funct3E, .Funct7E, .IntDivE, .MDUE, .W64E, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM, .Funct3E, .Funct7E, .IntDivE, .MDUE, .W64E, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM,
.CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M,
.RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM, .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM,
@ -105,7 +106,7 @@ module ieu (
datapath dp( datapath dp(
.clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE, .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE,
.ALUControlE, .Funct3E, .Funct7E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .JumpE, .BranchSignedE, .ALUControlE, .Funct3E, .Funct7E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .JumpE, .BranchSignedE,
.PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BSelectE,
.StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW, .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW,
.StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW, .StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW,
.CSRReadValW, .MDUResultW, .FIntDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW); .CSRReadValW, .MDUResultW, .FIntDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW);