forked from Github_Repos/cvw
Flow updated for 90nm
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Teo Ene
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3
.gitmodules
vendored
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[submodule "sky130/sky130_osu_sc_t12"]
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path = sky130/sky130_osu_sc_t12
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url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12/
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Subproject commit f60f2d0395053c4df362a97d7e2099721b6face6
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@ -1,195 +0,0 @@
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///////////////////////////////////////////
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// lzd.sv
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//
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// Written: James.Stine@okstate.edu 1 February 2021
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// Modified:
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//
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// Purpose: Integer Divide instructions
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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/* verilator lint_off DECLFILENAME */
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// Original idea came from V. G. Oklobdzija, "An algorithmic and novel
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// design of a leading zero detector circuit: comparison with logic
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// synthesis," in IEEE Transactions on Very Large Scale Integration
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// (VLSI) Systems, vol. 2, no. 1, pp. 124-128, March 1994, doi:
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// 10.1109/92.273153.
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// Modified to be more hierarchical
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module lz2 (P, V, B);
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input logic [1:0] B;
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output logic P;
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output logic V;
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assign V = B[0] | B[1];
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assign P = B[0] & ~B[1];
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endmodule // lz2
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module lzd_hier #(parameter WIDTH=8)
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(input logic [WIDTH-1:0] B,
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output logic [$clog2(WIDTH)-1:0] ZP,
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output logic ZV);
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if (WIDTH == 128)
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lz128 lzd127 (ZP, ZV, B);
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else if (WIDTH == 64)
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lz64 lzd64 (ZP, ZV, B);
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else if (WIDTH == 32)
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lz32 lzd32 (ZP, ZV, B);
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else if (WIDTH == 16)
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lz16 lzd16 (ZP, ZV, B);
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else if (WIDTH == 8)
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lz8 lzd8 (ZP, ZV, B);
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else if (WIDTH == 4)
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lz4 lzd4 (ZP, ZV, B);
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endmodule // lzd_hier
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module lz4 (ZP, ZV, B);
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input logic [3:0] B;
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logic ZPa;
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logic ZPb;
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logic ZVa;
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logic ZVb;
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output logic [1:0] ZP;
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output logic ZV;
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lz2 l1(ZPa, ZVa, B[1:0]);
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lz2 l2(ZPb, ZVb, B[3:2]);
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assign ZP[0:0] = ZVb ? ZPb : ZPa;
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assign ZP[1] = ~ZVb;
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assign ZV = ZVa | ZVb;
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endmodule
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module lz8 (ZP, ZV, B);
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input logic [7:0] B;
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logic [1:0] ZPa;
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logic [1:0] ZPb;
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logic ZVa;
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logic ZVb;
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output logic [2:0] ZP;
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output logic ZV;
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lz4 l1(ZPa, ZVa, B[3:0]);
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lz4 l2(ZPb, ZVb, B[7:4]);
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assign ZP[1:0] = ZVb ? ZPb : ZPa;
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assign ZP[2] = ~ZVb;
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assign ZV = ZVa | ZVb;
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endmodule
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module lz16 (ZP, ZV, B);
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input logic [15:0] B;
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logic [2:0] ZPa;
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logic [2:0] ZPb;
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logic ZVa;
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logic ZVb;
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output logic [3:0] ZP;
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output logic ZV;
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lz8 l1(ZPa, ZVa, B[7:0]);
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lz8 l2(ZPb, ZVb, B[15:8]);
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assign ZP[2:0] = ZVb ? ZPb : ZPa;
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assign ZP[3] = ~ZVb;
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assign ZV = ZVa | ZVb;
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endmodule // lz16
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module lz32 (ZP, ZV, B);
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input logic [31:0] B;
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logic [3:0] ZPa;
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logic [3:0] ZPb;
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logic ZVa;
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logic ZVb;
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output logic [4:0] ZP;
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output logic ZV;
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lz16 l1(ZPa, ZVa, B[15:0]);
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lz16 l2(ZPb, ZVb, B[31:16]);
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assign ZP[3:0] = ZVb ? ZPb : ZPa;
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assign ZP[4] = ~ZVb;
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assign ZV = ZVa | ZVb;
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endmodule // lz32
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module lz64 (ZP, ZV, B);
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input logic [63:0] B;
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logic [4:0] ZPa;
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logic [4:0] ZPb;
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logic ZVa;
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logic ZVb;
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output logic [5:0] ZP;
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output logic ZV;
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lz32 l1(ZPa, ZVa, B[31:0]);
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lz32 l2(ZPb, ZVb, B[63:32]);
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assign ZP[4:0] = ZVb ? ZPb : ZPa;
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assign ZP[5] = ~ZVb;
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assign ZV = ZVa | ZVb;
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endmodule // lz64
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module lz128 (ZP, ZV, B);
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input logic [127:0] B;
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logic [5:0] ZPa;
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logic [5:0] ZPb;
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logic ZVa;
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logic ZVb;
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output logic [6:0] ZP;
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output logic ZV;
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lz64 l1(ZPa, ZVa, B[64:0]);
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lz64 l2(ZPb, ZVb, B[127:63]);
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assign ZP[5:0] = ZVb ? ZPb : ZPa;
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assign ZP[6] = ~ZVb;
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assign ZV = ZVa | ZVb;
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endmodule // lz128
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/* verilator lint_on DECLFILENAME */
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