forked from Github_Repos/cvw
riscvsingle reparittioned to match Ch4
This commit is contained in:
David Harris
parent
55b4423329
commit
ebf9f5d526
@ -12,12 +12,12 @@ add wave /testbench/reset
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add wave -divider "Main Datapath"
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add wave /testbench/dut/PC
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add wave /testbench/dut/Instr
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add wave /testbench/dut/rvsingle/dp/SrcA
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add wave /testbench/dut/rvsingle/dp/SrcB
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add wave /testbench/dut/rvsingle/dp/Result
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add wave /testbench/dut/ieu/dp/SrcA
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add wave /testbench/dut/ieu/dp/SrcB
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add wave /testbench/dut/ieu/dp/Result
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add wave -divider "Memory Bus"
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add wave /testbench/MemWrite
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add wave /testbench/DataAdr
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add wave /testbench/IEUAdr
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add wave /testbench/WriteData
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run -all
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run 210
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view wave
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@ -1,20 +1,45 @@
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///////////////////////////////////////////
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// riscvsingle.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Simplified Single Cycle RISC-V Processor
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// Adapted from DDCA RISC-V Edition
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// Modified to match partitioning in RISC-V SoC Design
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// RISC-V single-cycle processor
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// From Section 7.6 of Digital Design & Computer Architecture
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// 27 April 2020
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// David_Harris@hmc.edu
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// Sarah.Harris@unlv.edu
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// run 210
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// Expect simulator to print "Simulation succeeded"
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// when the value 25 (0x19) is written to address 100 (0x64)
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// Single-cycle implementation of RISC-V (RV32I)
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// User-level Instruction Set Architecture V2.2 (May 7, 2017)
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// User-level Instruction Set Architecture V2.2
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// Implements a subset of the base integer instructions:
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// lw, sw
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// add, sub, and, or, slt,
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// add, sub, and, or, slt
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// addi, andi, ori, slti
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// beq
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// jal
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@ -78,37 +103,39 @@
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// sw 0100011 010 immediate
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// jal 1101111 immediate immediate
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module testbench();
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/* verilator lint_on UNUSED */
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/* verilator lint_off COMBDLY */
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/* verilator lint_off INITIALDLY */
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/* verilator lint_off STMTDLY */
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module testbench();
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logic clk;
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logic reset;
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logic [31:0] WriteData, DataAdr;
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logic [31:0] WriteData, IEUAdr;
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logic MemWrite;
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// instantiate device to be tested
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top dut(clk, reset, WriteData, DataAdr, MemWrite);
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riscvsinglehart dut(clk, reset, WriteData, IEUAdr, MemWrite);
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// initialize test
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initial
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begin
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initial begin
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reset <= 1; # 22; reset <= 0;
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end
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// generate clock to sequence tests
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always
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begin
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always begin
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clk <= 1; # 5; clk <= 0; # 5;
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end
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// check results
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always @(negedge clk)
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begin
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always @(negedge clk) begin
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if(MemWrite) begin
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if(DataAdr === 100 & WriteData === 25) begin
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if(IEUAdr === 100 & WriteData === 25) begin
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$display("Simulation succeeded");
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$stop;
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end else if (DataAdr !== 96) begin
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end else if (IEUAdr !== 96) begin
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$display("Simulation failed");
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$stop;
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end
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@ -116,155 +143,148 @@ module testbench();
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end
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endmodule
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module top(input logic clk, reset,
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output logic [31:0] WriteData, DataAdr,
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module riscvsinglehart(
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input logic clk, reset,
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output logic [31:0] WriteData, IEUAdr,
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output logic MemWrite);
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logic [31:0] PC, Instr, ReadData;
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logic [31:0] PC, PCPlus4, Instr, ReadData;
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logic PCSrc;
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// instantiate processor and memories
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riscvsingle rvsingle(clk, reset, PC, Instr, MemWrite, DataAdr,
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WriteData, ReadData);
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imem imem(PC, Instr);
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dmem dmem(clk, MemWrite, DataAdr, WriteData, ReadData);
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ifu ifu(.clk, .reset, .PCSrc, .IEUAdr, .Instr, .PC, .PCPlus4);
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ieu ieu(.clk, .reset, .Instr, .PC, .PCPlus4, .PCSrc, .MemWrite, .IEUAdr, .WriteData, .ReadData);
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lsu lsu(.clk, .MemWrite, .IEUAdr, .WriteData, .ReadData);
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endmodule
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module riscvsingle(input logic clk, reset,
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output logic [31:0] PC,
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input logic [31:0] Instr,
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output logic MemWrite,
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output logic [31:0] ALUResult, WriteData,
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input logic [31:0] ReadData);
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module ifu(
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input logic clk, reset,
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input logic PCSrc,
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input logic [31:0] IEUAdr,
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output logic [31:0] Instr, PC, PCPlus4);
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logic ALUSrc, RegWrite, Jump, Zero;
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logic [1:0] ResultSrc, ImmSrc;
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logic [2:0] ALUControl;
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controller c(Instr[6:0], Instr[14:12], Instr[30], Zero,
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ResultSrc, MemWrite, PCSrc,
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ALUSrc, RegWrite, Jump,
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ImmSrc, ALUControl);
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datapath dp(clk, reset, ResultSrc, PCSrc,
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ALUSrc, RegWrite,
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ImmSrc, ALUControl,
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Zero, PC, Instr,
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ALUResult, WriteData, ReadData);
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endmodule
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module controller(input logic [6:0] op,
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input logic [2:0] funct3,
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input logic funct7b5,
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input logic Zero,
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output logic [1:0] ResultSrc,
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output logic MemWrite,
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output logic PCSrc, ALUSrc,
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output logic RegWrite, Jump,
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output logic [1:0] ImmSrc,
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output logic [2:0] ALUControl);
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logic [1:0] ALUOp;
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logic Branch;
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maindec md(op, ResultSrc, MemWrite, Branch,
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ALUSrc, RegWrite, Jump, ImmSrc, ALUOp);
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aludec ad(op[5], funct3, funct7b5, ALUOp, ALUControl);
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assign PCSrc = Branch & Zero | Jump;
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endmodule
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module maindec(input logic [6:0] op,
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output logic [1:0] ResultSrc,
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output logic MemWrite,
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output logic Branch, ALUSrc,
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output logic RegWrite, Jump,
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output logic [1:0] ImmSrc,
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output logic [1:0] ALUOp);
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logic [10:0] controls;
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assign {RegWrite, ImmSrc, ALUSrc, MemWrite,
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ResultSrc, Branch, ALUOp, Jump} = controls;
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always_comb
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case(op)
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// RegWrite_ImmSrc_ALUSrc_MemWrite_ResultSrc_Branch_ALUOp_Jump
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7'b0000011: controls = 11'b1_00_1_0_01_0_00_0; // lw
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7'b0100011: controls = 11'b0_01_1_1_00_0_00_0; // sw
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7'b0110011: controls = 11'b1_xx_0_0_00_0_10_0; // R-type
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7'b1100011: controls = 11'b0_10_0_0_00_1_01_0; // beq
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7'b0010011: controls = 11'b1_00_1_0_00_0_10_0; // I-type ALU
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7'b1101111: controls = 11'b1_11_0_0_10_0_00_1; // jal
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default: controls = 11'bx_xx_x_x_xx_x_xx_x; // non-implemented instruction
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endcase
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endmodule
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module aludec(input logic opb5,
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input logic [2:0] funct3,
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input logic funct7b5,
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input logic [1:0] ALUOp,
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output logic [2:0] ALUControl);
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logic RtypeSub;
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assign RtypeSub = funct7b5 & opb5; // TRUE for R-type subtract instruction
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always_comb
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case(ALUOp)
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2'b00: ALUControl = 3'b000; // addition
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2'b01: ALUControl = 3'b001; // subtraction
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default: case(funct3) // R-type or I-type ALU
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3'b000: if (RtypeSub)
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ALUControl = 3'b001; // sub
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else
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ALUControl = 3'b000; // add, addi
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3'b010: ALUControl = 3'b101; // slt, slti
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3'b110: ALUControl = 3'b011; // or, ori
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3'b111: ALUControl = 3'b010; // and, andi
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default: ALUControl = 3'bxxx; // ???
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endcase
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endcase
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endmodule
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module datapath(input logic clk, reset,
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input logic [1:0] ResultSrc,
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input logic PCSrc, ALUSrc,
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input logic RegWrite,
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input logic [1:0] ImmSrc,
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input logic [2:0] ALUControl,
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output logic Zero,
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output logic [31:0] PC,
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input logic [31:0] Instr,
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output logic [31:0] ALUResult, WriteData,
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input logic [31:0] ReadData);
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logic [31:0] PCNext, PCPlus4, PCTarget;
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logic [31:0] ImmExt;
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logic [31:0] SrcA, SrcB;
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logic [31:0] Result;
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logic [31:0] PCNext;
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// next PC logic
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flopr #(32) pcreg(clk, reset, PCNext, PC);
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adder pcadd4(PC, 32'd4, PCPlus4);
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adder pcaddbranch(PC, ImmExt, PCTarget);
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mux2 #(32) pcmux(PCPlus4, PCTarget, PCSrc, PCNext);
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// register file logic
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regfile rf(clk, RegWrite, Instr[19:15], Instr[24:20],
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Instr[11:7], Result, SrcA, WriteData);
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extend ext(Instr[31:7], ImmSrc, ImmExt);
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// ALU logic
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mux2 #(32) srcbmux(WriteData, ImmExt, ALUSrc, SrcB);
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alu alu(SrcA, SrcB, ALUControl, ALUResult, Zero);
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mux3 #(32) resultmux(ALUResult, ReadData, PCPlus4, ResultSrc, Result);
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mux2 #(32) pcmux(PCPlus4, IEUAdr, PCSrc, PCNext);
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irom irom(PC, Instr);
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endmodule
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module regfile(input logic clk,
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input logic we3,
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input logic [ 4:0] a1, a2, a3,
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input logic [31:0] wd3,
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output logic [31:0] rd1, rd2);
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module irom(input logic [31:0] a,
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output logic [31:0] rd);
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logic [31:0] rf[31:0];
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logic [31:0] RAM[63:0];
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initial
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$readmemh("riscvtest.memfile",RAM);
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assign rd = RAM[a[7:2]]; // word aligned
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endmodule
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module ieu(
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input logic clk, reset,
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input logic [31:0] Instr,
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input logic [31:0] PC, PCPlus4,
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output logic PCSrc, MemWrite,
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output logic [31:0] IEUAdr, WriteData,
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input logic [31:0] ReadData);
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logic RegWrite, Jump, Eq, ALUResultSrc, ResultSrc;
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logic [1:0] ALUSrc, ImmSrc;
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logic [1:0] ALUControl;
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controller c(.Op(Instr[6:0]), .Funct3(Instr[14:12]), .Funct7b5(Instr[30]), .Eq,
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.ALUResultSrc, .ResultSrc, .MemWrite, .PCSrc,
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.ALUSrc, .RegWrite, .ImmSrc, .ALUControl);
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datapath dp(.clk, .reset, .Funct3(Instr[14:12]),
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.ALUResultSrc, .ResultSrc, .ALUSrc, .RegWrite, .ImmSrc, .ALUControl, .Eq,
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.PC, .PCPlus4, .Instr, .IEUAdr, .WriteData, .ReadData);
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endmodule
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module controller(
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input logic [6:0] Op,
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input logic Eq,
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input logic [2:0] Funct3,
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input logic Funct7b5,
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output logic ALUResultSrc,
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output logic ResultSrc,
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output logic MemWrite,
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output logic PCSrc,
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output logic RegWrite,
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output logic [1:0] ALUSrc, ImmSrc,
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output logic [1:0] ALUControl);
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logic Branch, Jump;
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logic Sub, ALUOp;
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logic [10:0] controls;
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// Main decoder
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always_comb
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case(Op)
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// RegWrite_ImmSrc_ALUSrc_ALUOp_ALUResultSrc_MemWrite_ResultSrc_Branch_Jump
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7'b0000011: controls = 11'b1_00_01_0_0_0_1_0_0; // lw
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7'b0100011: controls = 11'b0_01_01_0_0_1_0_0_0; // sw
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7'b0110011: controls = 11'b1_xx_00_1_0_0_0_0_0; // R-type
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7'b1100011: controls = 11'b0_10_11_0_0_0_0_1_0; // beq
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7'b0010011: controls = 11'b1_00_01_1_0_0_0_0_0; // I-type ALU
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7'b1101111: controls = 11'b1_11_11_0_1_0_0_0_1; // jal
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default: controls = 11'bx_xx_xx_x_x_x_x_x_x; // non-implemented instruction
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endcase
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assign {RegWrite, ImmSrc, ALUSrc, ALUOp, ALUResultSrc, MemWrite,
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ResultSrc, Branch, Jump} = controls;
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// ALU Control Logic
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assign Sub = ALUOp & ((Funct3 == 3'b000) & Funct7b5 & Op[5] | (Funct3 == 3'b010)); // subtract or SLT
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assign ALUControl = {Sub, ALUOp};
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// PCSrc logic
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assign PCSrc = Branch & Eq | Jump;
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endmodule
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module datapath(
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input logic clk, reset,
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input logic [2:0] Funct3,
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input logic ALUResultSrc, ResultSrc,
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input logic [1:0] ALUSrc,
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input logic RegWrite,
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input logic [1:0] ImmSrc,
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input logic [1:0] ALUControl,
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output logic Eq,
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input logic [31:0] PC, PCPlus4,
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input logic [31:0] Instr,
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output logic [31:0] IEUAdr, WriteData,
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input logic [31:0] ReadData);
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logic [31:0] ImmExt;
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logic [31:0] R1, R2, SrcA, SrcB;
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logic [31:0] ALUResult, IEUResult, Result;
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// register file logic
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regfile rf(.clk, .WE3(RegWrite), .A1(Instr[19:15]), .A2(Instr[24:20]),
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.A3(Instr[11:7]), .WD3(Result), .RD1(R1), .RD2(R2));
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extend ext(.Instr(Instr[31:7]), .ImmSrc, .ImmExt);
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// ALU logic
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cmp cmp(.R1, .R2, .Eq);
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mux2 #(32) srcamux(R1, PC, ALUSrc[1], SrcA);
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mux2 #(32) srcbmux(R2, ImmExt, ALUSrc[0], SrcB);
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alu alu(.SrcA, .SrcB, .ALUControl, .Funct3, .ALUResult, .IEUAdr);
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mux2 #(32) ieuresultmux(ALUResult, PCPlus4, ALUResultSrc, IEUResult);
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mux2 #(32) resultmux(IEUResult, ReadData, ResultSrc, Result);
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assign WriteData = R2;
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endmodule
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module regfile(
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input logic clk,
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input logic WE3,
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input logic [ 4:0] A1, A2, A3,
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input logic [31:0] WD3,
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output logic [31:0] RD1, RD2);
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logic [31:0] rf[31:1];
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// three ported register file
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// read two ports combinationally (A1/RD1, A2/RD2)
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@ -272,38 +292,89 @@ module regfile(input logic clk,
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// register 0 hardwired to 0
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always_ff @(posedge clk)
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if (we3) rf[a3] <= wd3;
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if (WE3) rf[A3] <= WD3;
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assign rd1 = (a1 != 0) ? rf[a1] : 0;
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assign rd2 = (a2 != 0) ? rf[a2] : 0;
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assign RD1 = (A1 != 0) ? rf[A1] : 0;
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assign RD2 = (A2 != 0) ? rf[A2] : 0;
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endmodule
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module adder(input [31:0] a, b,
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output [31:0] y);
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assign y = a + b;
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endmodule
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module extend(input logic [31:7] instr,
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input logic [1:0] immsrc,
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output logic [31:0] immext);
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module extend(
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input logic [31:7] Instr,
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input logic [1:0] ImmSrc,
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output logic [31:0] ImmExt);
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always_comb
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case(immsrc)
|
||||
case(ImmSrc)
|
||||
// I-type
|
||||
2'b00: immext = {{20{instr[31]}}, instr[31:20]};
|
||||
2'b00: ImmExt = {{20{Instr[31]}}, Instr[31:20]};
|
||||
// S-type (stores)
|
||||
2'b01: immext = {{20{instr[31]}}, instr[31:25], instr[11:7]};
|
||||
2'b01: ImmExt = {{20{Instr[31]}}, Instr[31:25], Instr[11:7]};
|
||||
// B-type (branches)
|
||||
2'b10: immext = {{20{instr[31]}}, instr[7], instr[30:25], instr[11:8], 1'b0};
|
||||
2'b10: ImmExt = {{20{Instr[31]}}, Instr[7], Instr[30:25], Instr[11:8], 1'b0};
|
||||
// J-type (jal)
|
||||
2'b11: immext = {{12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0};
|
||||
default: immext = 32'bx; // undefined
|
||||
2'b11: ImmExt = {{12{Instr[31]}}, Instr[19:12], Instr[20], Instr[30:21], 1'b0};
|
||||
default: ImmExt = 32'bx; // undefined
|
||||
endcase
|
||||
endmodule
|
||||
|
||||
module flopr #(parameter WIDTH = 8)
|
||||
(input logic clk, reset,
|
||||
module cmp(
|
||||
input logic [31:0] R1, R2,
|
||||
output logic Eq
|
||||
);
|
||||
|
||||
assign Eq = (R1 == R2);
|
||||
endmodule
|
||||
|
||||
|
||||
module alu(
|
||||
input logic [31:0] SrcA, SrcB,
|
||||
input logic [1:0] ALUControl,
|
||||
input logic [2:0] Funct3,
|
||||
output logic [31:0] ALUResult, IEUAdr);
|
||||
|
||||
logic [31:0] CondInvb, Sum, SLT;
|
||||
logic ALUOp, Sub, Overflow, Neg, LT;
|
||||
logic [2:0] ALUFunct;
|
||||
|
||||
assign {Sub, ALUOp} = ALUControl;
|
||||
|
||||
// Add or subtract
|
||||
assign CondInvb = Sub ? ~SrcB : SrcB;
|
||||
assign Sum = SrcA + CondInvb + Sub;
|
||||
assign IEUAdr = Sum; // Send this out to IFU and LSU
|
||||
|
||||
// Set less than based on subtraction result
|
||||
assign Overflow = (SrcA[31] ^ SrcB[31]) & (SrcA[31] ^ Sum[31]);
|
||||
assign Neg = Sum[31];
|
||||
assign LT = Neg ^ Overflow;
|
||||
assign SLT = {31'b0, LT};
|
||||
|
||||
assign ALUFunct = Funct3 & {3{ALUOp}}; // Force ALUFunct to 0 to Add when ALUOp = 0
|
||||
always_comb
|
||||
case (ALUFunct)
|
||||
3'b000: ALUResult = Sum; // add or sub
|
||||
3'b010: ALUResult = SLT; // slt
|
||||
3'b110: ALUResult = SrcA | SrcB; // or
|
||||
3'b111: ALUResult = SrcA & SrcB; // and
|
||||
default: ALUResult = 'x;
|
||||
endcase
|
||||
endmodule
|
||||
|
||||
module lsu(
|
||||
input logic clk, MemWrite,
|
||||
input logic [31:0] IEUAdr, WriteData,
|
||||
output logic [31:0] ReadData);
|
||||
|
||||
logic [31:0] RAM[63:0];
|
||||
|
||||
assign ReadData = RAM[IEUAdr[7:2]]; // word aligned
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (MemWrite) RAM[IEUAdr[7:2]] <= WriteData;
|
||||
endmodule
|
||||
|
||||
module flopr #(parameter WIDTH = 8) (
|
||||
input logic clk, reset,
|
||||
input logic [WIDTH-1:0] d,
|
||||
output logic [WIDTH-1:0] q);
|
||||
|
||||
@ -312,73 +383,17 @@ module flopr #(parameter WIDTH = 8)
|
||||
else q <= d;
|
||||
endmodule
|
||||
|
||||
module mux2 #(parameter WIDTH = 8)
|
||||
(input logic [WIDTH-1:0] d0, d1,
|
||||
module mux2 #(parameter WIDTH = 8) (
|
||||
input logic [WIDTH-1:0] d0, d1,
|
||||
input logic s,
|
||||
output logic [WIDTH-1:0] y);
|
||||
|
||||
assign y = s ? d1 : d0;
|
||||
endmodule
|
||||
|
||||
module mux3 #(parameter WIDTH = 8)
|
||||
(input logic [WIDTH-1:0] d0, d1, d2,
|
||||
input logic [1:0] s,
|
||||
output logic [WIDTH-1:0] y);
|
||||
module adder(input [31:0] a, b,
|
||||
output [31:0] y);
|
||||
|
||||
assign y = s[1] ? d2 : (s[0] ? d1 : d0);
|
||||
assign y = a + b;
|
||||
endmodule
|
||||
|
||||
module imem(input logic [31:0] a,
|
||||
output logic [31:0] rd);
|
||||
|
||||
logic [31:0] RAM[63:0];
|
||||
|
||||
initial
|
||||
$readmemh("riscvtest.memfile",RAM);
|
||||
|
||||
assign rd = RAM[a[31:2]]; // word aligned
|
||||
endmodule
|
||||
|
||||
module dmem(input logic clk, we,
|
||||
input logic [31:0] a, wd,
|
||||
output logic [31:0] rd);
|
||||
|
||||
logic [31:0] RAM[63:0];
|
||||
|
||||
assign rd = RAM[a[31:2]]; // word aligned
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (we) RAM[a[31:2]] <= wd;
|
||||
endmodule
|
||||
|
||||
module alu(input logic [31:0] a, b,
|
||||
input logic [2:0] alucontrol,
|
||||
output logic [31:0] result,
|
||||
output logic zero);
|
||||
|
||||
logic [31:0] condinvb, sum;
|
||||
logic v; // overflow
|
||||
logic isAddSub; // true when is add or subtract operation
|
||||
|
||||
assign condinvb = alucontrol[0] ? ~b : b;
|
||||
assign sum = a + condinvb + alucontrol[0];
|
||||
assign isAddSub = ~alucontrol[2] & ~alucontrol[1] |
|
||||
~alucontrol[1] & alucontrol[0];
|
||||
|
||||
always_comb
|
||||
case (alucontrol)
|
||||
3'b000: result = sum; // add
|
||||
3'b001: result = sum; // subtract
|
||||
3'b010: result = a & b; // and
|
||||
3'b011: result = a | b; // or
|
||||
3'b100: result = a ^ b; // xor
|
||||
3'b101: result = sum[31] ^ v; // slt
|
||||
3'b110: result = a << b[4:0]; // sll
|
||||
3'b111: result = a >> b[4:0]; // srl
|
||||
default: result = 32'bx;
|
||||
endcase
|
||||
|
||||
assign zero = (result == 32'b0);
|
||||
assign v = ~(alucontrol[0] ^ a[31] ^ b[31]) & (a[31] ^ sum[31]) & isAddSub;
|
||||
|
||||
endmodule
|
||||
|
||||
@ -9,7 +9,7 @@ make clean:
|
||||
make all:
|
||||
# *** Build old tests/imperas-riscv-tests for now;
|
||||
# Delete this part when the privileged tests transition over to tests/wally-riscv-arch-test
|
||||
# Also delete exe2memfile at that point
|
||||
# Also delete bin/exe2memfile at that point
|
||||
make -C ../../tests/imperas-riscv-tests
|
||||
make -C ../../tests/imperas-riscv-tests XLEN=64
|
||||
cd ../../tests/imperas-riscv-tests; exe2memfile.pl work/*/*.elf
|
||||
|
||||
Loading…
Reference in New Issue
Block a user