Updated tests for fpga and BP.

pipelined/regression/wally-pipelined.do

@@ -67,8 +67,8 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
 
 } elseif {$2 eq "fpga"} {
     echo "hello"
-    vlog  -work work_fpga +incdir+../config/fpga +incdir+../config/shared ../testbench/testbench.sv ../testbench/sdc/*.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv  ../../fpga/sim/*.sv -suppress 8852,12070,3084,3829,2583,7063
+    vlog  -work work +incdir+../config/fpga +incdir+../config/shared ../testbench/testbench.sv ../testbench/sdc/*.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv  ../../fpga/sim/*.sv -suppress 8852,12070,3084,3829,2583,7063
-    vopt +acc work_fpga.testbench -G TEST=$2 -G DEBUG=0 -o workopt     
+    vopt +acc work.testbench -G TEST=$2 -G DEBUG=0 -o workopt     
     vsim workopt +nowarn3829  -fatal 7
     
     do fpga-wave.do

pipelined/testbench/testbench.sv

@@ -159,7 +159,7 @@ logic [3:0] dummy;
   assign UARTSin = 1;
 
   if(`EXT_MEM_SUPPORTED) begin
-    ram #(.BASE(`EXT_MEM_BASE), .RANGE(`EXT_MEM_RANGE)) 
+    ram_ahb #(.BASE(`EXT_MEM_BASE), .RANGE(`EXT_MEM_RANGE)) 
     ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT), 
          .HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY,
          .HWSTRB);
@@ -226,9 +226,9 @@ logic [3:0] dummy;
       else memfilename = {pathname, tests[test], ".elf.memfile"};
       if (`FPGA) begin
         string romfilename, sdcfilename;
-        romfilename = {"../../tests/testsBP/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
+        romfilename = {"../../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
         sdcfilename = {"../testbench/sdc/ramdisk2.hex"};   
-        $readmemh(romfilename, dut.wallypipelinedsoc.uncore.uncore.bootrom.bootrom.memory.RAM);
+        $readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
         $readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
         // force sdc timers
         force dut.uncore.uncore.sdc.SDC.LimitTimers = 1;

pipelined/testbench/tests.vh

@@ -29,6 +29,7 @@
 `define MYIMPERASTEST   "3"
 `define COREMARK "4"
 `define EMBENCH "5"
+`define CUSTOM "6"
 // *** remove MYIMPERASTEST cases when ported 
 
 string tvpaths[] = '{
@@ -37,7 +38,8 @@ string tvpaths[] = '{
     "../../tests/riscof/work/wally-riscv-arch-test/",
     "../../tests/imperas-riscv-tests/work/",
     "../../benchmarks/coremark/work/",
-    "../../addins/embench-iot/"
+    "../../addins/embench-iot/",
+    "../../tests/custom/work/"
     };
 
   string coremark[] = '{
@@ -874,7 +876,6 @@ string imperas32f[] = '{
 
   string testsBP64[] = '{
     `IMPERASTEST,
-    "rv64BP/floating-point-bug",
     "rv64BP/simple"
 //    "rv64BP/mmm",
 //    "rv64BP/linpack_bench",
@@ -1927,10 +1928,15 @@ string imperas32f[] = '{
  };
 
  string fpga[] = '{
-    `WALLYTEST,
+    `CUSTOM,
     "NULL"
  };
 
+ string custom[] = '{
+    `CUSTOM,
+    "simple"
+ };
+
  string ahb[] = '{
     `RISCVARCHTEST,
     "rv64i_m/F/src/fadd_b11-01.S"

tests/custom/fpga-test-sdc/Makefile

@@ -108,5 +108,5 @@ $(TARGET).memfile: $(TARGET)
 	@echo 'Making memory file'
 	riscv64-unknown-elf-elf2hex --bit-width 64 --input $^ --output $@
 	extractFunctionRadix.sh $<.objdump
-	mkdir -p ../../imperas-riscv-tests/work/rv64BP/
+	mkdir -p ../work/
-	cp -f $(TARGETDIR)/* ../../imperas-riscv-tests/work/rv64BP/
+	cp -f $(TARGETDIR)/* ../work/

tests/custom/simple/Makefile

@@ -6,7 +6,7 @@ LIBRARY_FILES	:= crt0
 
 MARCH           :=-march=rv64imfdc
 MABI            :=-mabi=lp64d
-LINKER          := ${ROOT}/linker8000-0000.x
+LINKER          := ${ROOT}/linker1000.x
 LINK_FLAGS      :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map
 
 CFLAGS =$(MARCH) $(MABI) -Wa,-alhs -Wa,-L -mcmodel=medany  -mstrict-align -O2