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fdiv cleanup, reduce number of rv32f fma_b15 tests being run to speed up regression

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David Harris 2022-12-30 06:40:25 -08:00
parent ef37070eee
commit e9b314f902
3 changed files with 9 additions and 12 deletions
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1
pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv
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@ -69,7 +69,6 @@ module fdivsqrtfsm(
assign ISpecialCaseE = AZeroE | BZeroE; // *** why is AZeroE part of this. Should other special cases be considered? assign ISpecialCaseE = AZeroE | BZeroE; // *** why is AZeroE part of this. Should other special cases be considered?
assign SpecialCaseE = MDUE ? ISpecialCaseE : FSpecialCaseE; assign SpecialCaseE = MDUE ? ISpecialCaseE : FSpecialCaseE;
end else assign SpecialCaseE = FSpecialCaseE; end else assign SpecialCaseE = FSpecialCaseE;
//flopenr #(1) SpecialCaseReg(clk, reset, ~StallM, SpecialCaseE, SpecialCaseM); // save SpecialCase for checking in fdivsqrtpostproc
flopenr #(1) SpecialCaseReg(clk, reset, IFDivStartE, SpecialCaseE, SpecialCaseM); // save SpecialCase for checking in fdivsqrtpostproc flopenr #(1) SpecialCaseReg(clk, reset, IFDivStartE, SpecialCaseE, SpecialCaseM); // save SpecialCase for checking in fdivsqrtpostproc
// DIVN = `NF+3 // DIVN = `NF+3

16
pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
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@ -157,13 +157,6 @@ module fdivsqrtpostproc(
end else begin end else begin
NormShiftM = ((`DIVBLEN+1)'(`DIVb) - (nM * (`DIVBLEN+1)'(`LOGR))); NormShiftM = ((`DIVBLEN+1)'(`DIVb) - (nM * (`DIVBLEN+1)'(`LOGR)));
PreResultM = IntQuotM; PreResultM = IntQuotM;
/*
if (~ALTBM & NegQuotM) begin
PreResultM = {3'b111, -IntQuotM};
end else begin
PreResultM = {3'b000, IntQuotM};
end*/
//PreResultM = {IntQuotM[`DIVb], IntQuotM[`DIVb], IntQuotM[`DIVb], IntQuotM}; // Suspicious Sign Extender
end end
@ -171,7 +164,12 @@ module fdivsqrtpostproc(
assign PreFPIntDivResultM = $signed(PreResultM >>> NormShiftM); assign PreFPIntDivResultM = $signed(PreResultM >>> NormShiftM);
assign SpecialFPIntDivResultM = BZeroM ? (RemOpM ? AM : {(`XLEN){1'b1}}) : PreFPIntDivResultM[`XLEN-1:0]; // special cases assign SpecialFPIntDivResultM = BZeroM ? (RemOpM ? AM : {(`XLEN){1'b1}}) : PreFPIntDivResultM[`XLEN-1:0]; // special cases
// *** conditional on RV64
assign FPIntDivResultM = (W64M ? {{(`XLEN-32){SpecialFPIntDivResultM[31]}}, SpecialFPIntDivResultM[31:0]} : SpecialFPIntDivResultM[`XLEN-1:0]); // Sign extending in case of W64 // sign extend result for W64
if (`XLEN==64)
assign FPIntDivResultM = (W64M ? {{(`XLEN-32){SpecialFPIntDivResultM[31]}}, SpecialFPIntDivResultM[31:0]} :
SpecialFPIntDivResultM[`XLEN-1:0]); // Sign extending in case of W64
else
assign FPIntDivResultM = SpecialFPIntDivResultM[`XLEN-1:0];
end end
endmodule endmodule

4
pipelined/testbench/tests.vh
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@ -1098,7 +1098,7 @@ string imperas32f[] = '{
"rv64i_m/F/src/flw-align-01.S", "rv64i_m/F/src/flw-align-01.S",
"rv64i_m/F/src/fmadd_b1-01.S", "rv64i_m/F/src/fmadd_b1-01.S",
"rv64i_m/F/src/fmadd_b14-01.S", "rv64i_m/F/src/fmadd_b14-01.S",
"rv64i_m/F/src/fmadd_b15-01.S", //"rv64i_m/F/src/fmadd_b15-01.S",
"rv64i_m/F/src/fmadd_b16-01.S", "rv64i_m/F/src/fmadd_b16-01.S",
"rv64i_m/F/src/fmadd_b17-01.S", "rv64i_m/F/src/fmadd_b17-01.S",
"rv64i_m/F/src/fmadd_b18-01.S", "rv64i_m/F/src/fmadd_b18-01.S",
@ -1473,7 +1473,7 @@ string imperas32f[] = '{
"rv32i_m/F/src/fmin_b19-01.S", "rv32i_m/F/src/fmin_b19-01.S",
"rv32i_m/F/src/fmsub_b1-01.S", "rv32i_m/F/src/fmsub_b1-01.S",
"rv32i_m/F/src/fmsub_b14-01.S", "rv32i_m/F/src/fmsub_b14-01.S",
"rv32i_m/F/src/fmsub_b15-01.S", //"rv32i_m/F/src/fmsub_b15-01.S",
"rv32i_m/F/src/fmsub_b16-01.S", "rv32i_m/F/src/fmsub_b16-01.S",
"rv32i_m/F/src/fmsub_b17-01.S", "rv32i_m/F/src/fmsub_b17-01.S",
"rv32i_m/F/src/fmsub_b18-01.S", "rv32i_m/F/src/fmsub_b18-01.S",