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Fixed mem write checking

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now passes around 50 instructions!
This commit is contained in:
Noah Boorstin 2021-01-25 20:06:13 -05:00
parent 358393a1da
commit e92db93939
2 changed files with 9 additions and 4 deletions
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3
wally-pipelined/regression/wally-busybear.do
View File

@ -53,6 +53,7 @@ add wave -hex /testbench_busybear/MemRWM[0]
add wave -hex /testbench_busybear/MemRWM[1] add wave -hex /testbench_busybear/MemRWM[1]
add wave -hex /testbench_busybear/ByteMaskM add wave -hex /testbench_busybear/ByteMaskM
add wave -hex /testbench_busybear/WriteDataM add wave -hex /testbench_busybear/WriteDataM
add wave -hex /testbench_busybear/DataAdrM
add wave -hex /testbench_busybear/dut/dp/regf/rf[1] add wave -hex /testbench_busybear/dut/dp/regf/rf[1]
add wave -hex /testbench_busybear/dut/dp/regf/rf[2] add wave -hex /testbench_busybear/dut/dp/regf/rf[2]
add wave -hex /testbench_busybear/dut/dp/regf/rf[3] add wave -hex /testbench_busybear/dut/dp/regf/rf[3]
@ -128,6 +129,6 @@ add wave /testbench_busybear/InstrWName
#set DefaultRadix hexadecimal #set DefaultRadix hexadecimal
# #
#-- Run the Simulation #-- Run the Simulation
run 700 run 800
#run -all #run -all
##quit ##quit

10
wally-pipelined/testbench/testbench-busybear.sv
View File

@ -103,14 +103,18 @@ module testbench_busybear();
end end
end end
logic [`XLEN-1:0] writeDataExpected; logic [`XLEN-1:0] writeDataExpected, writeAdrExpected;
// this might need to change // this might need to change
always @(WriteDataM or DataAdrM or ByteMaskM) begin always @(WriteDataM or DataAdrM or ByteMaskM) begin
#1;
if (MemRWM[0]) begin if (MemRWM[0]) begin
$display("!!!!");
scan_file_memW = $fscanf(data_file_memW, "%x\n", writeDataExpected); scan_file_memW = $fscanf(data_file_memW, "%x\n", writeDataExpected);
scan_file_memW = $fscanf(data_file_memW, "%x\n", writeAdrExpected);
if (writeDataExpected != WriteDataM) begin if (writeDataExpected != WriteDataM) begin
$display("%t ps: WriteDataM does not equal WriteDataExpected: %x, %x", $time, WriteDataM, writeDataExpected); $display("%t ps: WriteDataM does not equal writeDataExpected: %x, %x", $time, WriteDataM, writeDataExpected);
end
if (writeAdrExpected != DataAdrM) begin
$display("%t ps: DataAdrM does not equal writeAdrExpected: %x, %x", $time, DataAdrM, writeAdrExpected);
end end
end end
end end