forked from Github_Repos/cvw
Routed CommittedM and PendingInterruptM through the lsu arb.
This commit is contained in:
Ross Thompson
parent
adce800041
commit
e91501985c
@ -7,37 +7,44 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/Func
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
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add wave -noupdate -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM
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add wave -noupdate -group {Memory Stage} /testbench/dut/hart/PCM
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add wave -noupdate -group {Memory Stage} /testbench/InstrMName
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add wave -noupdate -group {Memory Stage} /testbench/dut/hart/InstrM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/DCacheStall
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
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add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
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@ -130,6 +137,7 @@ add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/zero
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu
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add wave -noupdate /testbench/dut/hart/lsu/dcache/WriteDataM
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E
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@ -147,12 +155,12 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/Write
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
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add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
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add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF
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add wave -noupdate -group PCS /testbench/dut/hart/PCF
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add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD
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add wave -noupdate -group PCS /testbench/dut/hart/PCE
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add wave -noupdate -group PCS /testbench/dut/hart/PCM
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add wave -noupdate -group PCS /testbench/PCW
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add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCNextF
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add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF
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add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD
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add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE
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add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM
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add wave -noupdate -expand -group PCS /testbench/PCW
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/InstrD
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcAE
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add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcBE
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@ -239,22 +247,22 @@ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
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@ -278,6 +286,7 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/ReadDataWEn
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add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
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add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
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add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW
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@ -333,20 +342,20 @@ add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPi
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add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsOut
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add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsEn
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add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOIntr
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HCLK
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HSELCLINT
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HADDR
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HWRITE
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HWDATA
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADY
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HTRANS
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADCLINT
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HRESPCLINT
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADYCLINT
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM
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add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HCLK
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add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HSELCLINT
|
||||
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HADDR
|
||||
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HWRITE
|
||||
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HWDATA
|
||||
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HREADY
|
||||
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HTRANS
|
||||
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HREADCLINT
|
||||
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HRESPCLINT
|
||||
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HREADYCLINT
|
||||
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME
|
||||
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP
|
||||
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM
|
||||
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM
|
||||
add wave -noupdate -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState
|
||||
add wave -noupdate -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall
|
||||
add wave -noupdate -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWRead
|
||||
@ -401,7 +410,7 @@ add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim
|
||||
add wave -noupdate /testbench/dut/uncore/dtim/memwrite
|
||||
add wave -noupdate /testbench/dut/uncore/dtim/HWDATA
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 12} {5675 ns} 0} {{Cursor 4} {1979605 ns} 0} {{Cursor 5} {6253401 ns} 0}
|
||||
WaveRestoreCursors {{Cursor 12} {718836 ns} 0} {{Cursor 4} {8790617 ns} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 297
|
||||
@ -417,4 +426,4 @@ configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {5566 ns} {5750 ns}
|
||||
WaveRestoreZoom {718645 ns} {719057 ns}
|
||||
|
||||
@ -147,6 +147,10 @@ module lsu
|
||||
|
||||
logic CacheableM;
|
||||
|
||||
logic CommittedMfromDCache;
|
||||
logic PendingInterruptMtoDCache;
|
||||
|
||||
|
||||
pagetablewalker pagetablewalker(
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
@ -188,6 +192,8 @@ module lsu
|
||||
.Funct3M(Funct3M),
|
||||
.AtomicM(AtomicM),
|
||||
.MemAdrM(MemAdrM),
|
||||
.CommittedM(CommittedM),
|
||||
.PendingInterruptM(PendingInterruptM),
|
||||
.StallW(StallW),
|
||||
.ReadDataW(ReadDataW),
|
||||
.SquashSCW(SquashSCW),
|
||||
@ -203,6 +209,8 @@ module lsu
|
||||
.SquashSCWfromDCache(SquashSCWfromDCache),
|
||||
.DataMisalignedMfromDCache(DataMisalignedMfromDCache),
|
||||
.ReadDataWfromDCache(ReadDataWfromDCache),
|
||||
.CommittedMfromDCache(CommittedMfromDCache),
|
||||
.PendingInterruptMtoDCache(PendingInterruptMtoDCache),
|
||||
.DCacheStall(DCacheStall));
|
||||
|
||||
|
||||
@ -320,9 +328,9 @@ module lsu
|
||||
.WriteDataM(WriteDataM),
|
||||
.ReadDataW(ReadDataWfromDCache),
|
||||
.DCacheStall(DCacheStall),
|
||||
.CommittedM(CommittedM),
|
||||
.CommittedM(CommittedMfromDCache),
|
||||
.ExceptionM(ExceptionM),
|
||||
.PendingInterruptM(PendingInterruptM),
|
||||
.PendingInterruptM(PendingInterruptMtoDCache),
|
||||
.DTLBMissM(DTLBMissM),
|
||||
.CacheableM(CacheableM),
|
||||
|
||||
|
||||
@ -43,20 +43,25 @@ module lsuArb
|
||||
input logic [1:0] AtomicM,
|
||||
input logic [`XLEN-1:0] MemAdrM,
|
||||
input logic StallW,
|
||||
input logic PendingInterruptM,
|
||||
// to CPU
|
||||
output logic [`XLEN-1:0] ReadDataW,
|
||||
output logic SquashSCW,
|
||||
output logic DataMisalignedM,
|
||||
output logic CommittedM,
|
||||
output logic LSUStall,
|
||||
|
||||
// to LSU
|
||||
// to D Cache
|
||||
output logic DisableTranslation,
|
||||
output logic [1:0] MemRWMtoDCache,
|
||||
output logic [2:0] Funct3MtoDCache,
|
||||
output logic [1:0] AtomicMtoDCache,
|
||||
output logic [`XLEN-1:0] MemAdrMtoDCache,
|
||||
output logic StallWtoDCache,
|
||||
// from LSU
|
||||
output logic PendingInterruptMtoDCache,
|
||||
|
||||
// from D Cache
|
||||
input logic CommittedMfromDCache,
|
||||
input logic SquashSCWfromDCache,
|
||||
input logic DataMisalignedMfromDCache,
|
||||
input logic [`XLEN-1:0] ReadDataWfromDCache,
|
||||
@ -82,7 +87,6 @@ module lsuArb
|
||||
|
||||
statetype CurrState, NextState;
|
||||
logic SelPTW;
|
||||
logic HPTWStallD;
|
||||
logic [2:0] PTWSize;
|
||||
|
||||
|
||||
@ -142,6 +146,8 @@ module lsuArb
|
||||
assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM;
|
||||
assign MemAdrMtoDCache = SelPTW ? HPTWPAdr : MemAdrM;
|
||||
assign StallWtoDCache = SelPTW ? 1'b0 : StallW;
|
||||
// always block interrupts when using the hardware page table walker.
|
||||
assign CommittedM = SelPTW ? 1'b1 : CommittedMfromDCache;
|
||||
|
||||
// demux the inputs from LSU to walker or cpu's data port.
|
||||
|
||||
@ -153,14 +159,8 @@ module lsuArb
|
||||
// not clear at all. I think it should be LSUStall from the LSU,
|
||||
// which is demuxed to HPTWStall and CPUDataStall? (not sure on this last one).
|
||||
assign HPTWStall = SelPTW ? DCacheStall : 1'b1;
|
||||
//assign HPTWStallD = SelPTW ? DataStall : 1'b1;
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
assign HPTWStallD = SelPTW ? DataStall : 1'b1;
|
||||
flopr #(1) HPTWStallReg (.clk(clk),
|
||||
.reset(reset),
|
||||
.d(HPTWStallD),
|
||||
.q(HPTWStall));
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
|
||||
assign PendingInterruptMtoDCache = SelPTW ? 1'b0 : PendingInterruptM;
|
||||
|
||||
assign LSUStall = SelPTW ? 1'b1 : DCacheStall; // *** this is probably going to change.
|
||||
|
||||
|
||||
@ -539,11 +539,11 @@ string tests32f[] = '{
|
||||
else if (TESTSPRIV)
|
||||
tests = tests64p;
|
||||
else begin
|
||||
tests = {tests64p,tests64i,tests64periph};
|
||||
tests = {tests64p,tests64i};
|
||||
if (`C_SUPPORTED) tests = {tests, tests64ic};
|
||||
else tests = {tests, tests64iNOc};
|
||||
if (`M_SUPPORTED) tests = {tests, tests64m};
|
||||
if (`A_SUPPORTED) tests = {tests, tests64a};
|
||||
//if (`A_SUPPORTED) tests = {tests, tests64a};
|
||||
if (`MEM_VIRTMEM) tests = {tests, tests64mmu};
|
||||
if (`F_SUPPORTED) tests = {tests64f, tests};
|
||||
if (`D_SUPPORTED) tests = {tests64d, tests};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user