forked from Github_Repos/cvw
Routed CommittedM and PendingInterruptM through the lsu arb.
This commit is contained in:
Ross Thompson
parent
adce800041
commit
e91501985c
@ -7,37 +7,44 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/Func
|
|||||||
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
|
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
|
||||||
add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
|
add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
|
||||||
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
|
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
|
add wave -noupdate -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
|
add wave -noupdate -group {Memory Stage} /testbench/dut/hart/PCM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
|
add wave -noupdate -group {Memory Stage} /testbench/InstrMName
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
|
add wave -noupdate -group {Memory Stage} /testbench/dut/hart/InstrM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
|
||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
|
||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
|
||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
|
||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
|
||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
|
add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
|
||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
|
add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
|
||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall
|
add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
|
||||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
|
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE
|
||||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
|
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
|
||||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD
|
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM
|
||||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE
|
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/TrapM
|
||||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM
|
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD
|
||||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW
|
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF
|
||||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
|
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/DCacheStall
|
||||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
|
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/MulDivStallD
|
||||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
|
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
|
||||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
|
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
|
||||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
|
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
|
||||||
|
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
|
||||||
|
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
|
||||||
|
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
|
||||||
|
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
|
||||||
|
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
|
||||||
|
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
|
||||||
|
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
|
||||||
add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
|
add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
|
||||||
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
|
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
|
||||||
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
|
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
|
||||||
@ -130,6 +137,7 @@ add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/zero
|
|||||||
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg
|
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg
|
||||||
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt
|
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt
|
||||||
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu
|
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu
|
||||||
|
add wave -noupdate /testbench/dut/hart/lsu/dcache/WriteDataM
|
||||||
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
|
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
|
||||||
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
|
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
|
||||||
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E
|
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E
|
||||||
@ -147,12 +155,12 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/Write
|
|||||||
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
|
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
|
||||||
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
|
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
|
||||||
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
|
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
|
||||||
add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF
|
add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCNextF
|
||||||
add wave -noupdate -group PCS /testbench/dut/hart/PCF
|
add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF
|
||||||
add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD
|
add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD
|
||||||
add wave -noupdate -group PCS /testbench/dut/hart/PCE
|
add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE
|
||||||
add wave -noupdate -group PCS /testbench/dut/hart/PCM
|
add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM
|
||||||
add wave -noupdate -group PCS /testbench/PCW
|
add wave -noupdate -expand -group PCS /testbench/PCW
|
||||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/InstrD
|
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/InstrD
|
||||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcAE
|
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcAE
|
||||||
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcBE
|
add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcBE
|
||||||
@ -239,22 +247,22 @@ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/
|
|||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
|
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
|
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
|
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable}
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid}
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty}
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr}
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr}
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData}
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits}
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits}
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
|
||||||
@ -278,6 +286,7 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU
|
|||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
|
||||||
|
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/ReadDataWEn
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
|
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
|
add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW
|
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW
|
||||||
@ -333,20 +342,20 @@ add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPi
|
|||||||
add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsOut
|
add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsOut
|
||||||
add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsEn
|
add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsEn
|
||||||
add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOIntr
|
add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOIntr
|
||||||
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HCLK
|
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HCLK
|
||||||
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HSELCLINT
|
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HSELCLINT
|
||||||
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HADDR
|
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HADDR
|
||||||
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HWRITE
|
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HWRITE
|
||||||
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HWDATA
|
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HWDATA
|
||||||
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADY
|
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HREADY
|
||||||
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HTRANS
|
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HTRANS
|
||||||
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADCLINT
|
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HREADCLINT
|
||||||
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HRESPCLINT
|
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HRESPCLINT
|
||||||
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADYCLINT
|
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HREADYCLINT
|
||||||
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME
|
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME
|
||||||
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP
|
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP
|
||||||
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM
|
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM
|
||||||
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM
|
add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM
|
||||||
add wave -noupdate -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState
|
add wave -noupdate -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState
|
||||||
add wave -noupdate -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall
|
add wave -noupdate -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall
|
||||||
add wave -noupdate -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWRead
|
add wave -noupdate -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWRead
|
||||||
@ -401,7 +410,7 @@ add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim
|
|||||||
add wave -noupdate /testbench/dut/uncore/dtim/memwrite
|
add wave -noupdate /testbench/dut/uncore/dtim/memwrite
|
||||||
add wave -noupdate /testbench/dut/uncore/dtim/HWDATA
|
add wave -noupdate /testbench/dut/uncore/dtim/HWDATA
|
||||||
TreeUpdate [SetDefaultTree]
|
TreeUpdate [SetDefaultTree]
|
||||||
WaveRestoreCursors {{Cursor 12} {5675 ns} 0} {{Cursor 4} {1979605 ns} 0} {{Cursor 5} {6253401 ns} 0}
|
WaveRestoreCursors {{Cursor 12} {718836 ns} 0} {{Cursor 4} {8790617 ns} 0}
|
||||||
quietly wave cursor active 1
|
quietly wave cursor active 1
|
||||||
configure wave -namecolwidth 250
|
configure wave -namecolwidth 250
|
||||||
configure wave -valuecolwidth 297
|
configure wave -valuecolwidth 297
|
||||||
@ -417,4 +426,4 @@ configure wave -griddelta 40
|
|||||||
configure wave -timeline 0
|
configure wave -timeline 0
|
||||||
configure wave -timelineunits ns
|
configure wave -timelineunits ns
|
||||||
update
|
update
|
||||||
WaveRestoreZoom {5566 ns} {5750 ns}
|
WaveRestoreZoom {718645 ns} {719057 ns}
|
||||||
|
|||||||
@ -146,6 +146,10 @@ module lsu
|
|||||||
logic DCacheStall;
|
logic DCacheStall;
|
||||||
|
|
||||||
logic CacheableM;
|
logic CacheableM;
|
||||||
|
|
||||||
|
logic CommittedMfromDCache;
|
||||||
|
logic PendingInterruptMtoDCache;
|
||||||
|
|
||||||
|
|
||||||
pagetablewalker pagetablewalker(
|
pagetablewalker pagetablewalker(
|
||||||
.clk(clk),
|
.clk(clk),
|
||||||
@ -188,6 +192,8 @@ module lsu
|
|||||||
.Funct3M(Funct3M),
|
.Funct3M(Funct3M),
|
||||||
.AtomicM(AtomicM),
|
.AtomicM(AtomicM),
|
||||||
.MemAdrM(MemAdrM),
|
.MemAdrM(MemAdrM),
|
||||||
|
.CommittedM(CommittedM),
|
||||||
|
.PendingInterruptM(PendingInterruptM),
|
||||||
.StallW(StallW),
|
.StallW(StallW),
|
||||||
.ReadDataW(ReadDataW),
|
.ReadDataW(ReadDataW),
|
||||||
.SquashSCW(SquashSCW),
|
.SquashSCW(SquashSCW),
|
||||||
@ -203,6 +209,8 @@ module lsu
|
|||||||
.SquashSCWfromDCache(SquashSCWfromDCache),
|
.SquashSCWfromDCache(SquashSCWfromDCache),
|
||||||
.DataMisalignedMfromDCache(DataMisalignedMfromDCache),
|
.DataMisalignedMfromDCache(DataMisalignedMfromDCache),
|
||||||
.ReadDataWfromDCache(ReadDataWfromDCache),
|
.ReadDataWfromDCache(ReadDataWfromDCache),
|
||||||
|
.CommittedMfromDCache(CommittedMfromDCache),
|
||||||
|
.PendingInterruptMtoDCache(PendingInterruptMtoDCache),
|
||||||
.DCacheStall(DCacheStall));
|
.DCacheStall(DCacheStall));
|
||||||
|
|
||||||
|
|
||||||
@ -320,9 +328,9 @@ module lsu
|
|||||||
.WriteDataM(WriteDataM),
|
.WriteDataM(WriteDataM),
|
||||||
.ReadDataW(ReadDataWfromDCache),
|
.ReadDataW(ReadDataWfromDCache),
|
||||||
.DCacheStall(DCacheStall),
|
.DCacheStall(DCacheStall),
|
||||||
.CommittedM(CommittedM),
|
.CommittedM(CommittedMfromDCache),
|
||||||
.ExceptionM(ExceptionM),
|
.ExceptionM(ExceptionM),
|
||||||
.PendingInterruptM(PendingInterruptM),
|
.PendingInterruptM(PendingInterruptMtoDCache),
|
||||||
.DTLBMissM(DTLBMissM),
|
.DTLBMissM(DTLBMissM),
|
||||||
.CacheableM(CacheableM),
|
.CacheableM(CacheableM),
|
||||||
|
|
||||||
|
|||||||
@ -43,20 +43,25 @@ module lsuArb
|
|||||||
input logic [1:0] AtomicM,
|
input logic [1:0] AtomicM,
|
||||||
input logic [`XLEN-1:0] MemAdrM,
|
input logic [`XLEN-1:0] MemAdrM,
|
||||||
input logic StallW,
|
input logic StallW,
|
||||||
|
input logic PendingInterruptM,
|
||||||
// to CPU
|
// to CPU
|
||||||
output logic [`XLEN-1:0] ReadDataW,
|
output logic [`XLEN-1:0] ReadDataW,
|
||||||
output logic SquashSCW,
|
output logic SquashSCW,
|
||||||
output logic DataMisalignedM,
|
output logic DataMisalignedM,
|
||||||
|
output logic CommittedM,
|
||||||
output logic LSUStall,
|
output logic LSUStall,
|
||||||
|
|
||||||
// to LSU
|
// to D Cache
|
||||||
output logic DisableTranslation,
|
output logic DisableTranslation,
|
||||||
output logic [1:0] MemRWMtoDCache,
|
output logic [1:0] MemRWMtoDCache,
|
||||||
output logic [2:0] Funct3MtoDCache,
|
output logic [2:0] Funct3MtoDCache,
|
||||||
output logic [1:0] AtomicMtoDCache,
|
output logic [1:0] AtomicMtoDCache,
|
||||||
output logic [`XLEN-1:0] MemAdrMtoDCache,
|
output logic [`XLEN-1:0] MemAdrMtoDCache,
|
||||||
output logic StallWtoDCache,
|
output logic StallWtoDCache,
|
||||||
// from LSU
|
output logic PendingInterruptMtoDCache,
|
||||||
|
|
||||||
|
// from D Cache
|
||||||
|
input logic CommittedMfromDCache,
|
||||||
input logic SquashSCWfromDCache,
|
input logic SquashSCWfromDCache,
|
||||||
input logic DataMisalignedMfromDCache,
|
input logic DataMisalignedMfromDCache,
|
||||||
input logic [`XLEN-1:0] ReadDataWfromDCache,
|
input logic [`XLEN-1:0] ReadDataWfromDCache,
|
||||||
@ -82,7 +87,6 @@ module lsuArb
|
|||||||
|
|
||||||
statetype CurrState, NextState;
|
statetype CurrState, NextState;
|
||||||
logic SelPTW;
|
logic SelPTW;
|
||||||
logic HPTWStallD;
|
|
||||||
logic [2:0] PTWSize;
|
logic [2:0] PTWSize;
|
||||||
|
|
||||||
|
|
||||||
@ -142,6 +146,8 @@ module lsuArb
|
|||||||
assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM;
|
assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM;
|
||||||
assign MemAdrMtoDCache = SelPTW ? HPTWPAdr : MemAdrM;
|
assign MemAdrMtoDCache = SelPTW ? HPTWPAdr : MemAdrM;
|
||||||
assign StallWtoDCache = SelPTW ? 1'b0 : StallW;
|
assign StallWtoDCache = SelPTW ? 1'b0 : StallW;
|
||||||
|
// always block interrupts when using the hardware page table walker.
|
||||||
|
assign CommittedM = SelPTW ? 1'b1 : CommittedMfromDCache;
|
||||||
|
|
||||||
// demux the inputs from LSU to walker or cpu's data port.
|
// demux the inputs from LSU to walker or cpu's data port.
|
||||||
|
|
||||||
@ -153,15 +159,9 @@ module lsuArb
|
|||||||
// not clear at all. I think it should be LSUStall from the LSU,
|
// not clear at all. I think it should be LSUStall from the LSU,
|
||||||
// which is demuxed to HPTWStall and CPUDataStall? (not sure on this last one).
|
// which is demuxed to HPTWStall and CPUDataStall? (not sure on this last one).
|
||||||
assign HPTWStall = SelPTW ? DCacheStall : 1'b1;
|
assign HPTWStall = SelPTW ? DCacheStall : 1'b1;
|
||||||
//assign HPTWStallD = SelPTW ? DataStall : 1'b1;
|
|
||||||
/* -----\/----- EXCLUDED -----\/-----
|
assign PendingInterruptMtoDCache = SelPTW ? 1'b0 : PendingInterruptM;
|
||||||
assign HPTWStallD = SelPTW ? DataStall : 1'b1;
|
|
||||||
flopr #(1) HPTWStallReg (.clk(clk),
|
|
||||||
.reset(reset),
|
|
||||||
.d(HPTWStallD),
|
|
||||||
.q(HPTWStall));
|
|
||||||
-----/\----- EXCLUDED -----/\----- */
|
|
||||||
|
|
||||||
assign LSUStall = SelPTW ? 1'b1 : DCacheStall; // *** this is probably going to change.
|
assign LSUStall = SelPTW ? 1'b1 : DCacheStall; // *** this is probably going to change.
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|||||||
@ -539,11 +539,11 @@ string tests32f[] = '{
|
|||||||
else if (TESTSPRIV)
|
else if (TESTSPRIV)
|
||||||
tests = tests64p;
|
tests = tests64p;
|
||||||
else begin
|
else begin
|
||||||
tests = {tests64p,tests64i,tests64periph};
|
tests = {tests64p,tests64i};
|
||||||
if (`C_SUPPORTED) tests = {tests, tests64ic};
|
if (`C_SUPPORTED) tests = {tests, tests64ic};
|
||||||
else tests = {tests, tests64iNOc};
|
else tests = {tests, tests64iNOc};
|
||||||
if (`M_SUPPORTED) tests = {tests, tests64m};
|
if (`M_SUPPORTED) tests = {tests, tests64m};
|
||||||
if (`A_SUPPORTED) tests = {tests, tests64a};
|
//if (`A_SUPPORTED) tests = {tests, tests64a};
|
||||||
if (`MEM_VIRTMEM) tests = {tests, tests64mmu};
|
if (`MEM_VIRTMEM) tests = {tests, tests64mmu};
|
||||||
if (`F_SUPPORTED) tests = {tests64f, tests};
|
if (`F_SUPPORTED) tests = {tests64f, tests};
|
||||||
if (`D_SUPPORTED) tests = {tests64d, tests};
|
if (`D_SUPPORTED) tests = {tests64d, tests};
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user