Branch predictor cleanup.

I think Ch 10 is now done except for BTB performance analysis and the section on running benchmarks and collecting data.
This commit is contained in:
Ross Thompson 2023-03-01 11:24:24 -06:00
parent 08a1153ae9
commit e8744684cd
3 changed files with 7 additions and 7 deletions

View File

@ -33,7 +33,7 @@ module RASPredictor #(parameter int StackSize = 16 )(
input logic clk, input logic clk,
input logic reset, input logic reset,
input logic StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM, input logic StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM,
input logic WrongBPReturnD, // Prediction class is wrong input logic BPReturnWrongD, // Prediction class is wrong
input logic ReturnD, input logic ReturnD,
input logic ReturnE, CallE, // Instr class input logic ReturnE, CallE, // Instr class
input logic BPReturnF, input logic BPReturnF,
@ -61,7 +61,7 @@ module RASPredictor #(parameter int StackSize = 16 )(
assign PopF = BPReturnF & ~StallD & ~FlushD; assign PopF = BPReturnF & ~StallD & ~FlushD;
assign PushE = CallE & ~StallM & ~FlushM; assign PushE = CallE & ~StallM & ~FlushM;
assign WrongPredReturnD = (WrongBPReturnD) & ~StallE & ~FlushE; assign WrongPredReturnD = (BPReturnWrongD) & ~StallE & ~FlushE;
assign FlushedReturnDE = (~StallE & FlushE & ReturnD) | (~StallM & FlushM & ReturnE); // flushed return assign FlushedReturnDE = (~StallE & FlushE & ReturnD) | (~StallM & FlushM & ReturnE); // flushed return
assign RepairD = WrongPredReturnD | FlushedReturnDE ; assign RepairD = WrongPredReturnD | FlushedReturnDE ;

View File

@ -95,7 +95,7 @@ module bpred (
logic ReturnE, CallE; logic ReturnE, CallE;
logic BranchM, JumpM, ReturnM, CallM; logic BranchM, JumpM, ReturnM, CallM;
logic BranchW, JumpW, ReturnW, CallW; logic BranchW, JumpW, ReturnW, CallW;
logic WrongBPReturnD; logic BPReturnWrongD;
logic [`XLEN-1:0] BTAE; logic [`XLEN-1:0] BTAE;
@ -163,12 +163,12 @@ module bpred (
icpred #(`INSTR_CLASS_PRED) icpred(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, icpred #(`INSTR_CLASS_PRED) icpred(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
.PostSpillInstrRawF, .InstrD, .BranchD, .BranchE, .JumpD, .JumpE, .BranchM, .BranchW, .JumpM, .JumpW, .PostSpillInstrRawF, .InstrD, .BranchD, .BranchE, .JumpD, .JumpE, .BranchM, .BranchW, .JumpM, .JumpW,
.CallD, .CallE, .CallM, .CallW, .ReturnD, .ReturnE, .ReturnM, .ReturnW, .BTBCallF, .BTBReturnF, .BTBJumpF, .CallD, .CallE, .CallM, .CallW, .ReturnD, .ReturnE, .ReturnM, .ReturnW, .BTBCallF, .BTBReturnF, .BTBJumpF,
.BTBBranchF, .BPCallF, .BPReturnF, .BPJumpF, .BPBranchF, .IClassWrongM, .IClassWrongE, .WrongBPReturnD); .BTBBranchF, .BPCallF, .BPReturnF, .BPJumpF, .BPBranchF, .IClassWrongM, .IClassWrongE, .BPReturnWrongD);
// Part 3 RAS // Part 3 RAS
RASPredictor RASPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, RASPredictor RASPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
.BPReturnF, .ReturnD, .ReturnE, .CallE, .BPReturnF, .ReturnD, .ReturnE, .CallE,
.WrongBPReturnD, .RASPCF, .PCLinkE); .BPReturnWrongD, .RASPCF, .PCLinkE);
// Check the prediction // Check the prediction
// if it is a CFI then check if the next instruction address (PCD) matches the branch's target or fallthrough address. // if it is a CFI then check if the next instruction address (PCD) matches the branch's target or fallthrough address.

View File

@ -42,7 +42,7 @@ module icpred #(parameter INSTR_CLASS_PRED = 1)(
output logic ReturnD, ReturnE, ReturnM, ReturnW, output logic ReturnD, ReturnE, ReturnM, ReturnW,
input logic BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF, input logic BTBCallF, BTBReturnF, BTBJumpF, BTBBranchF,
output logic BPCallF, BPReturnF, BPJumpF, BPBranchF, output logic BPCallF, BPReturnF, BPJumpF, BPBranchF,
output logic IClassWrongM, WrongBPReturnD, IClassWrongE output logic IClassWrongM, BPReturnWrongD, IClassWrongE
); );
logic IClassWrongD; logic IClassWrongD;
@ -101,6 +101,6 @@ module icpred #(parameter INSTR_CLASS_PRED = 1)(
// branch class prediction wrong. // branch class prediction wrong.
assign IClassWrongD = |({BPCallD, BPReturnD, BPJumpD, BPBranchD} ^ {CallD, ReturnD, JumpD, BranchD}); assign IClassWrongD = |({BPCallD, BPReturnD, BPJumpD, BPBranchD} ^ {CallD, ReturnD, JumpD, BranchD});
assign WrongBPReturnD = BPReturnD ^ ReturnD; assign BPReturnWrongD = BPReturnD ^ ReturnD;
endmodule endmodule