forked from Github_Repos/cvw
Renamed InstrFirstHalf to InstrFirstHalfF.
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@ -58,7 +58,7 @@ module spill #(
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logic SpillF;
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logic SelSpillF;
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logic SpillSaveF;
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logic [15:0] InstrFirstHalf;
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logic [15:0] InstrFirstHalfF;
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// PC logic
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@ -102,10 +102,10 @@ module spill #(
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// save the first 2 bytes
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flopenr #(16) SpillInstrReg(clk, reset, SpillSaveF, InstrRawF[15:0], InstrFirstHalf);
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flopenr #(16) SpillInstrReg(clk, reset, SpillSaveF, InstrRawF[15:0], InstrFirstHalfF);
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// merge together
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mux2 #(32) postspillmux(InstrRawF, {InstrRawF[15:0], InstrFirstHalf}, SpillF, PostSpillInstrRawF);
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mux2 #(32) postspillmux(InstrRawF, {InstrRawF[15:0], InstrFirstHalfF}, SpillF, PostSpillInstrRawF);
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// Need to use always comb to avoid pessimistic x propagation if PostSpillInstrRawF is x
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always_comb
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