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				@ -122,11 +122,14 @@ module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68) (
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     if(ce1) rd1 <= #1 mem[ra1]; */
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    // Write divided into part for bytes and part for extra msbs
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    // coverage off     
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    //   when byte write enables are tied high, the last IF is always taken
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    if(WIDTH >= 8) 
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      always @(posedge clk) 
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        if (ce2 & we2) 
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          for(i = 0; i < WIDTH/8; i++) 
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            if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8];
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    // coverage on
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    if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8
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      always @(posedge clk) 
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@ -62,7 +62,7 @@ module RASPredictor #(parameter int StackSize = 16 )(
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  assign PushE = CallE & ~StallM & ~FlushM;
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  assign WrongPredReturnD = (BPReturnWrongD) & ~StallE & ~FlushE;
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  assign FlushedReturnDE = (~StallE & FlushE & ReturnD) | (~StallM & FlushM & ReturnE); // flushed return
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  assign FlushedReturnDE = (~StallE & FlushE & ReturnD) | (FlushM & ReturnE); // flushed return
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  assign RepairD = WrongPredReturnD | FlushedReturnDE ;
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