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Merge pull request #220 from davidharrishmc/dev

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Obscure coverage fixes
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Ross Thompson 2023-04-08 10:27:31 -05:00 committed by GitHub
commit e79119e2fd
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2 changed files with 4 additions and 1 deletions
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3
src/generic/mem/ram2p1r1wbe.sv
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@ -122,11 +122,14 @@ module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68) (
if(ce1) rd1 <= #1 mem[ra1]; */ if(ce1) rd1 <= #1 mem[ra1]; */
// Write divided into part for bytes and part for extra msbs // Write divided into part for bytes and part for extra msbs
// coverage off
// when byte write enables are tied high, the last IF is always taken
if(WIDTH >= 8) if(WIDTH >= 8)
always @(posedge clk) always @(posedge clk)
if (ce2 & we2) if (ce2 & we2)
for(i = 0; i < WIDTH/8; i++) for(i = 0; i < WIDTH/8; i++)
if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8]; if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8];
// coverage on
if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8 if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8
always @(posedge clk) always @(posedge clk)

2
src/ifu/bpred/RASPredictor.sv
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@ -62,7 +62,7 @@ module RASPredictor #(parameter int StackSize = 16 )(
assign PushE = CallE & ~StallM & ~FlushM; assign PushE = CallE & ~StallM & ~FlushM;
assign WrongPredReturnD = (BPReturnWrongD) & ~StallE & ~FlushE; assign WrongPredReturnD = (BPReturnWrongD) & ~StallE & ~FlushE;
assign FlushedReturnDE = (~StallE & FlushE & ReturnD) | (~StallM & FlushM & ReturnE); // flushed return assign FlushedReturnDE = (~StallE & FlushE & ReturnD) | (FlushM & ReturnE); // flushed return
assign RepairD = WrongPredReturnD | FlushedReturnDE ; assign RepairD = WrongPredReturnD | FlushedReturnDE ;