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FPU remove unused signals

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This commit is contained in:
David Harris 2022-12-20 14:43:30 -08:00
parent caef1a6997
commit e7702e48b7
10 changed files with 15 additions and 27 deletions
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5
pipelined/regression/lint-wally
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@ -5,9 +5,10 @@ export PATH=$PATH:/usr/local/bin/
verilator=`which verilator` verilator=`which verilator`
basepath=$(dirname $0)/.. basepath=$(dirname $0)/..
for config in rv32e rv64gc rv32gc rv32ic rv32i rv64i rv64fpquad; do #for config in rv32e rv64gc rv32gc rv32ic rv32i rv64i rv64fpquad; do
for config in rv64gc; do
echo "$config linting..." echo "$config linting..."
if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes); then if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes --Wall); then
echo "Exiting after $config lint due to errors or warnings" echo "Exiting after $config lint due to errors or warnings"
exit 1 exit 1
fi fi

5
pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv
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@ -37,7 +37,7 @@ module fdivsqrtqsel2 (
); );
logic [3:0] p, g; logic [3:0] p, g;
logic magnitude, sign, cout; logic magnitude, sign;
logic pos, neg; logic pos, neg;
// The quotient selection logic is presented for simplicity, not // The quotient selection logic is presented for simplicity, not
@ -48,9 +48,6 @@ module fdivsqrtqsel2 (
assign p = ps ^ pc; assign p = ps ^ pc;
assign g = ps & pc; assign g = ps & pc;
//assign magnitude = ~(&p[2:0]);
assign cout = g[2] | (p[2] & (g[1] | p[1] & g[0]));
//assign sign = p[3] ^ cout;
assign magnitude = ~((ps[2]^pc[2]) & (ps[1]^pc[1]) & assign magnitude = ~((ps[2]^pc[2]) & (ps[1]^pc[1]) &
(ps[0]^pc[0])); (ps[0]^pc[0]));
assign sign = (ps[3]^pc[3])^ assign sign = (ps[3]^pc[3])^

3
pipelined/src/fpu/fma/fma.sv
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@ -41,7 +41,6 @@ module fma(
output logic ZmSticky, // sticky bit that is calculated during alignment output logic ZmSticky, // sticky bit that is calculated during alignment
output logic KillProd, // set the product to zero before addition if the product is too small to matter output logic KillProd, // set the product to zero before addition if the product is too small to matter
output logic [3*`NF+5:0] Sm, // the positive sum's significand output logic [3*`NF+5:0] Sm, // the positive sum's significand
output logic NegSum, // was the sum negitive
output logic InvA, // Was A inverted for effective subtraction (P-A or -P+A) output logic InvA, // Was A inverted for effective subtraction (P-A or -P+A)
output logic As, // the aligned addend's sign (modified Z sign for other opperations) output logic As, // the aligned addend's sign (modified Z sign for other opperations)
output logic Ps, // the product's sign output logic Ps, // the product's sign
@ -84,7 +83,7 @@ module fma(
// // Addition/LZA // // Addition/LZA
// /////////////////////////////////////////////////////////////////////////////// // ///////////////////////////////////////////////////////////////////////////////
fmaadd add(.Am, .Pm, .Ze, .Pe, .Ps, .As, .KillProd, .ZmSticky, .AmInv, .PmKilled, .NegSum, .InvA, .Sm, .Se, .Ss); fmaadd add(.Am, .Pm, .Ze, .Pe, .Ps, .As, .KillProd, .ZmSticky, .AmInv, .PmKilled, .InvA, .Sm, .Se, .Ss);
fmalza #(3*`NF+6) lza(.A(AmInv), .Pm({PmKilled, 1'b0, InvA&Ps&ZmSticky&KillProd}), .Cin(InvA & ~(ZmSticky & ~KillProd)), .sub(InvA), .SCnt); fmalza #(3*`NF+6) lza(.A(AmInv), .Pm({PmKilled, 1'b0, InvA&Ps&ZmSticky&KillProd}), .Cin(InvA & ~(ZmSticky & ~KillProd)), .sub(InvA), .SCnt);
endmodule endmodule

2
pipelined/src/fpu/fma/fmaadd.sv
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@ -41,12 +41,12 @@ module fmaadd(
input logic [`NE+1:0] Pe, input logic [`NE+1:0] Pe,
output logic [3*`NF+5:0] AmInv, // aligned addend possibly inverted output logic [3*`NF+5:0] AmInv, // aligned addend possibly inverted
output logic [2*`NF+1:0] PmKilled, // the product's mantissa possibly killed output logic [2*`NF+1:0] PmKilled, // the product's mantissa possibly killed
output logic NegSum, // was the sum negitive
output logic Ss, output logic Ss,
output logic [`NE+1:0] Se, output logic [`NE+1:0] Se,
output logic [3*`NF+5:0] Sm // the positive sum output logic [3*`NF+5:0] Sm // the positive sum
); );
logic [3*`NF+5:0] PreSum, NegPreSum; // possibly negitive sum logic [3*`NF+5:0] PreSum, NegPreSum; // possibly negitive sum
logic NegSum; // was the sum negitive
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////
// Addition // Addition

11
pipelined/src/fpu/fpu.sv
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@ -113,7 +113,6 @@ module fpu (
logic [`NE+1:0] SeE,SeM; logic [`NE+1:0] SeE,SeM;
logic KillProdE, KillProdM; logic KillProdE, KillProdM;
logic InvAE, InvAM; logic InvAE, InvAM;
logic NegSumE, NegSumM;
logic AsE, AsM; logic AsE, AsM;
logic PsE, PsM; logic PsE, PsM;
logic SsE, SsM; logic SsE, SsM;
@ -258,7 +257,7 @@ module fpu (
.OpCtrl(OpCtrlE), .Fmt(FmtE), .OpCtrl(OpCtrlE), .Fmt(FmtE),
.As(AsE), .Ps(PsE), .Ss(SsE), .Se(SeE), .As(AsE), .Ps(PsE), .Ss(SsE), .Se(SeE),
.Sm(SmE), .Pe(PeE), .Sm(SmE), .Pe(PeE),
.NegSum(NegSumE), .InvA(InvAE), .SCnt(SCntE), .InvA(InvAE), .SCnt(SCntE),
.ZmSticky(ZmStickyE), .KillProd(KillProdE)); .ZmSticky(ZmStickyE), .KillProd(KillProdE));
// divide and squareroot // divide and squareroot
@ -355,9 +354,9 @@ module fpu (
flopenrc #(1) EMRegCmpFlg (clk, reset, FlushM, ~StallM, PreNVE, PreNVM); flopenrc #(1) EMRegCmpFlg (clk, reset, FlushM, ~StallM, PreNVE, PreNVM);
flopenrc #(3*`NF+6) EMRegFma2(clk, reset, FlushM, ~StallM, SmE, SmM); flopenrc #(3*`NF+6) EMRegFma2(clk, reset, FlushM, ~StallM, SmE, SmM);
flopenrc #(`NE+2) EMRegFma3(clk, reset, FlushM, ~StallM, PeE, PeM); flopenrc #(`NE+2) EMRegFma3(clk, reset, FlushM, ~StallM, PeE, PeM);
flopenrc #($clog2(3*`NF+7)+9+`NE) EMRegFma4(clk, reset, FlushM, ~StallM, flopenrc #($clog2(3*`NF+7)+8+`NE) EMRegFma4(clk, reset, FlushM, ~StallM,
{ZmStickyE, KillProdE, InvAE, SCntE, NegSumE, AsE, PsE, SsE, SeE}, {ZmStickyE, KillProdE, InvAE, SCntE, AsE, PsE, SsE, SeE},
{ZmStickyM, KillProdM, InvAM, SCntM, NegSumM, AsM, PsM, SsM, SeM}); {ZmStickyM, KillProdM, InvAM, SCntM, AsM, PsM, SsM, SeM});
flopenrc #(`NE+`LOGCVTLEN+`CVTLEN+4) EMRegCvt(clk, reset, FlushM, ~StallM, flopenrc #(`NE+`LOGCVTLEN+`CVTLEN+4) EMRegCvt(clk, reset, FlushM, ~StallM,
{CeE, CvtShiftAmtE, CvtResDenormUfE, CsE, IntZeroE, CvtLzcInE}, {CeE, CvtShiftAmtE, CvtResDenormUfE, CsE, IntZeroE, CvtLzcInE},
{CeM, CvtShiftAmtM, CvtResDenormUfM, CsM, IntZeroM, CvtLzcInM}); {CeM, CvtShiftAmtM, CvtResDenormUfM, CsM, IntZeroM, CvtLzcInM});
@ -379,7 +378,7 @@ module fpu (
postprocess postprocess(.Xs(XsM), .Ys(YsM), .Ze(ZeM), .Xm(XmM), .Ym(YmM), .Zm(ZmM), .Frm(FrmM), .Fmt(FmtM), .FmaPe(PeM), postprocess postprocess(.Xs(XsM), .Ys(YsM), .Ze(ZeM), .Xm(XmM), .Ym(YmM), .Zm(ZmM), .Frm(FrmM), .Fmt(FmtM), .FmaPe(PeM),
.FmaZmS(ZmStickyM), .FmaKillProd(KillProdM), .XZero(XZeroM), .YZero(YZeroM), .ZZero(ZZeroM), .XInf(XInfM), .YInf(YInfM), .DivQm(QmM), .FmaSs(SsM), .FmaZmS(ZmStickyM), .FmaKillProd(KillProdM), .XZero(XZeroM), .YZero(YZeroM), .ZZero(ZZeroM), .XInf(XInfM), .YInf(YInfM), .DivQm(QmM), .FmaSs(SsM),
.ZInf(ZInfM), .XNaN(XNaNM), .YNaN(YNaNM), .ZNaN(ZNaNM), .XSNaN(XSNaNM), .YSNaN(YSNaNM), .ZSNaN(ZSNaNM), .FmaSm(SmM), .DivQe(QeM), /*.DivDone(DivDoneM), */ .ZInf(ZInfM), .XNaN(XNaNM), .YNaN(YNaNM), .ZNaN(ZNaNM), .XSNaN(XSNaNM), .YSNaN(YSNaNM), .ZSNaN(ZSNaNM), .FmaSm(SmM), .DivQe(QeM), /*.DivDone(DivDoneM), */
.FmaNegSum(NegSumM), .FmaInvA(InvAM), .ZDenorm(ZDenormM), .FmaAs(AsM), .FmaPs(PsM), .OpCtrl(OpCtrlM), .FmaSCnt(SCntM), .FmaSe(SeM), .ZDenorm(ZDenormM), .FmaAs(AsM), .FmaPs(PsM), .OpCtrl(OpCtrlM), .FmaSCnt(SCntM), .FmaSe(SeM),
.CvtCe(CeM), .CvtResDenormUf(CvtResDenormUfM),.CvtShiftAmt(CvtShiftAmtM), .CvtCs(CsM), .ToInt(FWriteIntM), .DivS(DivSM), .CvtCe(CeM), .CvtResDenormUf(CvtResDenormUfM),.CvtShiftAmt(CvtShiftAmtM), .CvtCs(CsM), .ToInt(FWriteIntM), .DivS(DivSM),
.CvtLzcIn(CvtLzcInM), .IntZero(IntZeroM), .PostProcSel(PostProcSelM), .PostProcRes(PostProcResM), .PostProcFlg(PostProcFlgM), .FCvtIntRes(FCvtIntResM)); .CvtLzcIn(CvtLzcInM), .IntZero(IntZeroM), .PostProcSel(PostProcSelM), .PostProcRes(PostProcResM), .PostProcFlg(PostProcFlgM), .FCvtIntRes(FCvtIntResM));

7
pipelined/src/fpu/postproc/postprocess.sv
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@ -52,8 +52,6 @@ module postprocess (
input logic [3*`NF+5:0] FmaSm, // the positive sum input logic [3*`NF+5:0] FmaSm, // the positive sum
input logic FmaZmS, // sticky bit that is calculated during alignment input logic FmaZmS, // sticky bit that is calculated during alignment
input logic FmaKillProd, // set the product to zero before addition if the product is too small to matter input logic FmaKillProd, // set the product to zero before addition if the product is too small to matter
input logic FmaNegSum, // was the sum negitive
input logic FmaInvA, // do you invert Z
input logic FmaSs, input logic FmaSs,
input logic [$clog2(3*`NF+7)-1:0] FmaSCnt, // the normalization shift count input logic [$clog2(3*`NF+7)-1:0] FmaSCnt, // the normalization shift count
//divide signals //divide signals
@ -196,8 +194,7 @@ module postprocess (
// round to nearest max magnitude // round to nearest max magnitude
roundsign roundsign(.FmaPs, .FmaAs, .FmaInvA, .FmaOp, .DivOp, .CvtOp, .FmaNegSum, roundsign roundsign(.FmaOp, .DivOp, .CvtOp, .Sqrt, .FmaSs, .Xs, .Ys, .CvtCs, .Ms);
.Sqrt, .FmaSs, .Xs, .Ys, .CvtCs, .Ms);
round round(.OutFmt, .Frm, .FmaZmS, .Plus1, .PostProcSel, .CvtCe, .Qe, round round(.OutFmt, .Frm, .FmaZmS, .Plus1, .PostProcSel, .CvtCe, .Qe,
.Ms, .FmaMe, .FmaOp, .CvtOp, .CvtResDenormUf, .Mf, .ToInt, .CvtResUf, .Ms, .FmaMe, .FmaOp, .CvtOp, .CvtResDenormUf, .Mf, .ToInt, .CvtResUf,
@ -208,7 +205,7 @@ module postprocess (
// Sign calculation // Sign calculation
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////
resultsign resultsign(.Frm, .FmaPs, .FmaAs, .FmaMe, .R, .S, .G, resultsign resultsign(.Frm, .FmaPs, .FmaAs, .R, .S, .G,
.FmaOp, .ZInf, .InfIn, .FmaSZero, .Mult, .Ms, .Ws); .FmaOp, .ZInf, .InfIn, .FmaSZero, .Mult, .Ms, .Ws);
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////

1
pipelined/src/fpu/postproc/resultsign.sv
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@ -35,7 +35,6 @@ module resultsign(
input logic ZInf, input logic ZInf,
input logic InfIn, input logic InfIn,
input logic FmaOp, input logic FmaOp,
input logic [`NE+1:0] FmaMe,
input logic FmaSZero, input logic FmaSZero,
input logic Mult, input logic Mult,
input logic R, input logic R,

3
pipelined/src/fpu/postproc/roundsign.sv
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@ -30,11 +30,8 @@
`include "wally-config.vh" `include "wally-config.vh"
module roundsign( module roundsign(
input logic FmaPs, FmaAs,
input logic FmaInvA,
input logic Xs, input logic Xs,
input logic Ys, input logic Ys,
input logic FmaNegSum,
input logic Sqrt, input logic Sqrt,
input logic FmaOp, input logic FmaOp,
input logic DivOp, input logic DivOp,

2
pipelined/src/ifu/spillsupport.sv
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@ -63,7 +63,7 @@ module spillsupport #(parameter CACHE_ENABLED)
mux2 #(`XLEN) pcplus2mux(.d0({PCF[`XLEN-1:2], 2'b10}), .d1({PCPlusUpperF, 2'b00}), .s(PCF[1]), .y(PCPlus2F)); mux2 #(`XLEN) pcplus2mux(.d0({PCF[`XLEN-1:2], 2'b10}), .d1({PCPlusUpperF, 2'b00}), .s(PCF[1]), .y(PCPlus2F));
// select between PCNextF and PCF+2 // select between PCNextF and PCF+2
mux2 #(`XLEN) pcnextspillmux(.d0(PCNextF), .d1(PCPlus2F), .s(SelNextSpillF & ~Flush), .y(PCNextFSpill)); mux2 #(`XLEN) pcnextspillmux(.d0(PCNextF), .d1(PCPlus2F), .s(SelNextSpillF & ~Flush), .y(PCNextFSpill));
// select between PCF adn PCF+2 // select between PCF and PCF+2
mux2 #(`XLEN) pcspillmux(.d0(PCF), .d1(PCPlus2F), .s(SelSpillF), .y(PCFSpill)); mux2 #(`XLEN) pcspillmux(.d0(PCF), .d1(PCPlus2F), .s(SelSpillF), .y(PCFSpill));
assign SpillF = &PCF[$clog2(SPILLTHRESHOLD)+1:1]; assign SpillF = &PCF[$clog2(SPILLTHRESHOLD)+1:1];

3
pipelined/src/uncore/uncore.sv
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@ -201,8 +201,7 @@ module uncore (
// takes more than 1 cycle to repsond it needs to hold on to the old select until the // takes more than 1 cycle to repsond it needs to hold on to the old select until the
// device is ready. Hense this register must be selectively enabled by HREADY. // device is ready. Hense this register must be selectively enabled by HREADY.
// However on reset None must be seleted. // However on reset None must be seleted.
flopenr #(10) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions[10:1], {HSELDTIMD, HSELIROMD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD}); flopenl #(11) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions, 11'b1, {HSELDTIMD, HSELIROMD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD, HSELNoneD});
flopenl #(1) hseldelayreg2(HCLK, ~HRESETn, HREADY, HSELRegions[0], 1'b1, HSELNoneD);
flopenr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HREADY, HSELBRIDGE, HSELBRIDGED); flopenr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HREADY, HSELBRIDGE, HSELBRIDGED);
endmodule endmodule