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slightly smarter dtim HREADY

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bbracker 2021-03-13 07:03:33 -05:00
parent 4757794887
commit e58d17d5b7
1 changed files with 6 additions and 1 deletions
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7
wally-pipelined/src/uncore/dtim.sv
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@ -40,6 +40,8 @@ module dtim #(parameter BASE=0, RANGE = 65535) (
logic [`XLEN-1:0] HREADTim0; logic [`XLEN-1:0] HREADTim0;
// logic [`XLEN-1:0] write; // logic [`XLEN-1:0] write;
logic [31:0] HADDRd;
logic newAdr;
logic [15:0] entry; logic [15:0] entry;
logic memread, memwrite; logic memread, memwrite;
logic [3:0] busycount; logic [3:0] busycount;
@ -48,14 +50,17 @@ module dtim #(parameter BASE=0, RANGE = 65535) (
memread <= HSELTim & ~ HWRITE; memread <= HSELTim & ~ HWRITE;
memwrite <= HSELTim & HWRITE; memwrite <= HSELTim & HWRITE;
A <= HADDR; A <= HADDR;
HADDRd <= HADDR;
end end
assign newAdr = HADDR!=HADDRd;
// busy FSM to extend READY signal // busy FSM to extend READY signal
always_ff @(posedge HCLK, negedge HRESETn) always_ff @(posedge HCLK, negedge HRESETn)
if (~HRESETn) begin if (~HRESETn) begin
HREADYTim <= 1; HREADYTim <= 1;
end else begin end else begin
if (HREADYTim & HSELTim) begin if ((HREADYTim | newAdr) & HSELTim) begin
busycount <= 0; busycount <= 0;
HREADYTim <= #1 0; HREADYTim <= #1 0;
end else if (~HREADYTim) begin end else if (~HREADYTim) begin