forked from Github_Repos/cvw
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
This commit is contained in:
David Harris
commit
e4b4800189
@ -186,7 +186,7 @@ add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState
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|||||||
add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState
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||||||
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM
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add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM
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add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/InstrReadF
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add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/InstrReadF
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add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/MemSizeM
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add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/LsuBusSize
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HCLK
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HCLK
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRESETn
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRESETn
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRDATA
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRDATA
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@ -203,163 +203,156 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HMASTLOCK
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
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add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
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add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/funct
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add wave -noupdate -expand -group lsu -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/InterlockCurrState
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add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/result
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add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/srca
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add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/srcb
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add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/width
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add wave -noupdate -expand -group lsu -color Gold /testbench/dut/hart/lsu/CurrState
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelHPTW
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelHPTW
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/InterlockStall
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/InterlockStall
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/LSUStall
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/LSUStall
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WalkerInstrPageFaultF
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataWordMuxM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WalkerInstrPageFaultRaw
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataM
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add wave -noupdate -expand -group lsu -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WriteDataM
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add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/WayHit
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelUncached
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add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
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add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState
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add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WayHit
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add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
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add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
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add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable
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add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
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add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM
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add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/ReadDataBlockM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
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add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/SelReplayCPURequest
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/ReadDataBlockM
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add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/IEUAdrE
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/MEM_VIRTMEM/SelReplayCPURequest
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add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/IEUAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrE
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add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/RAdr
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrM
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add wave -noupdate -expand -group lsu -group dcache -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/FlushAdr
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/RAdr
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add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/FlushWay
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add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/FlushAdr
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add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimDirtyWay
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add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/FlushWay
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add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimTag
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add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimDirtyWay
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add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/BasePAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimTag
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add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/FetchCount
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add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/BasePAdrM
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add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/CacheableM
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add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/CacheableM
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add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable}
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetValid}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetValid}
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetDirty}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetDirty}
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[0]/CacheTagMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[0]/CacheTagMem/StoredData}
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/DirtyBits}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/DirtyBits}
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ValidBits}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ValidBits}
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/DirtyBits}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/DirtyBits}
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ValidBits}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ValidBits}
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/SetDirty}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/SetDirty}
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteEnable}
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteWordEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteWordEnable}
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[1]/CacheTagMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[1]/CacheTagMem/StoredData}
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add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
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||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
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||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
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||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
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||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
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||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
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||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
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||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WriteEnable}
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||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetValid}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetValid}
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||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetDirty}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetDirty}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[2]/CacheTagMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[2]/CacheTagMem/StoredData}
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||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/DirtyBits}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/DirtyBits}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ValidBits}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ValidBits}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WriteEnable}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetValid}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetValid}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetDirty}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetDirty}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ClearDirty}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ClearDirty}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/VDWriteEnable}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/VDWriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[3]/CacheTagMem/StoredData}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[3]/CacheTagMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/DirtyBits}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/DirtyBits}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ValidBits}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ValidBits}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetValid
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetValid
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/RAdr
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/RAdr
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WayHit}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WayHit}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Valid}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Valid}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Dirty}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Dirty}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ReadTag}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ReadTag}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WayHit}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WayHit}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Valid}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Valid}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Dirty}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Dirty}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ReadTag}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ReadTag}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WayHit}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WayHit}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Valid}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Valid}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Dirty}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Dirty}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ReadTag}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ReadTag}
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordMuxM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordMuxM
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
|
||||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
|
||||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
|
||||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
|
||||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
|
||||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
|
||||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
|
||||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
|
||||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/FlushDCacheM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/FlushDCacheM
|
||||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
|
||||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataM
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/ReadDataWordM
|
||||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/FinalWriteDataM
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
|
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
|
add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/FetchCount
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCFetchLine
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCWriteLine
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrM
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BUSACK
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
|
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/FlushWay
|
||||||
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
|
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/VAdr
|
||||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/FlushWay
|
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||||
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/VAdr
|
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PTE
|
||||||
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
|
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/HitPageType
|
||||||
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PTE
|
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate
|
||||||
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/HitPageType
|
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
|
||||||
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate
|
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss
|
||||||
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
|
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit
|
||||||
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss
|
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress
|
||||||
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit
|
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/TLBPageFault
|
||||||
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress
|
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/LoadAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/TLBPageFault
|
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/StoreAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/LoadAccessFaultM
|
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBPAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/StoreAccessFaultM
|
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PTE
|
||||||
add wave -noupdate -expand -group lsu -expand -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBPAdr
|
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PageTypeWriteVal
|
||||||
add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PTE
|
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBWrite
|
||||||
add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PageTypeWriteVal
|
|
||||||
add wave -noupdate -expand -group lsu -expand -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBWrite
|
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PhysicalAddress
|
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PhysicalAddress
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/SelRegions
|
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/SelRegions
|
||||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Cacheable
|
add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Cacheable
|
||||||
@ -383,19 +376,16 @@ add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pm
|
|||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/W
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/W
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/X
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/X
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/L
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/L
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/genblk1/WalkerState
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/PCF
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PCF
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/genblk1/TranslationVAdr
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/genblk1/TranslationVAdr
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWReadPTE
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWReadPTE
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWAdr
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWAdr
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/PTE
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PTE
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/ITLBMissF
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBMissF
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/DTLBMissM
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBMissM
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/ITLBWriteF
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBWriteF
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/DTLBWriteM
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBWriteM
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF
|
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM
|
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM
|
|
||||||
add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
|
add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
|
||||||
add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
|
add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
|
||||||
add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
|
add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
|
||||||
@ -474,21 +464,8 @@ add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW
|
|||||||
add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PCNext2F
|
add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PCNext2F
|
||||||
add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedNextPCM
|
add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedNextPCM
|
||||||
add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedChangePCM
|
add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedChangePCM
|
||||||
add wave -noupdate /testbench/dut/hart/ifu/PCCorrectE
|
|
||||||
add wave -noupdate /testbench/dut/hart/ifu/PCSrcE
|
|
||||||
add wave -noupdate /testbench/dut/hart/ieu/c/BranchTakenE
|
|
||||||
add wave -noupdate /testbench/dut/hart/ieu/c/BranchE
|
|
||||||
add wave -noupdate /testbench/dut/hart/ifu/PCLinkE
|
|
||||||
add wave -noupdate /testbench/dut/hart/lsu/DCtoAHBSizeM
|
|
||||||
add wave -noupdate /testbench/dut/hart/ifu/PCF
|
|
||||||
add wave -noupdate /testbench/dut/uncore/uart/uart/u/LSR
|
|
||||||
add wave -noupdate /testbench/dut/uncore/uart/uart/u/DLM
|
|
||||||
add wave -noupdate /testbench/dut/uncore/uart/uart/u/DLAB
|
|
||||||
add wave -noupdate /testbench/dut/hart/ifu/temp
|
|
||||||
add wave -noupdate /testbench/dut/hart/ifu/BPPredWrongM
|
|
||||||
add wave -noupdate /testbench/dut/hart/ifu/InvalidateICacheM
|
|
||||||
TreeUpdate [SetDefaultTree]
|
TreeUpdate [SetDefaultTree]
|
||||||
WaveRestoreCursors {{Cursor 7} {31851 ns} 1} {{Cursor 5} {26638 ns} 0}
|
WaveRestoreCursors {{Cursor 7} {31851 ns} 1} {{Cursor 5} {207375 ns} 0}
|
||||||
quietly wave cursor active 2
|
quietly wave cursor active 2
|
||||||
configure wave -namecolwidth 250
|
configure wave -namecolwidth 250
|
||||||
configure wave -valuecolwidth 314
|
configure wave -valuecolwidth 314
|
||||||
@ -504,4 +481,4 @@ configure wave -griddelta 40
|
|||||||
configure wave -timeline 0
|
configure wave -timeline 0
|
||||||
configure wave -timelineunits ns
|
configure wave -timelineunits ns
|
||||||
update
|
update
|
||||||
WaveRestoreZoom {26532 ns} {26750 ns}
|
WaveRestoreZoom {207017 ns} {208185 ns}
|
||||||
|
|||||||
151
wally-pipelined/src/cache/dcache.sv
vendored
151
wally-pipelined/src/cache/dcache.sv
vendored
@ -27,40 +27,41 @@
|
|||||||
|
|
||||||
module dcache
|
module dcache
|
||||||
(input logic clk,
|
(input logic clk,
|
||||||
input logic reset,
|
input logic reset,
|
||||||
input logic CPUBusy,
|
input logic CPUBusy,
|
||||||
|
|
||||||
// cpu side
|
// cpu side
|
||||||
input logic [1:0] MemRWM,
|
input logic [1:0] MemRWM,
|
||||||
input logic [2:0] Funct3M,
|
input logic [2:0] Funct3M,
|
||||||
input logic [6:0] Funct7M,
|
input logic [6:0] Funct7M,
|
||||||
input logic [1:0] AtomicM,
|
input logic [1:0] AtomicM,
|
||||||
input logic FlushDCacheM,
|
input logic FlushDCacheM,
|
||||||
input logic [11:0] MemAdrE, // virtual address, but we only use the lower 12 bits.
|
input logic [11:0] MemAdrE, // virtual address, but we only use the lower 12 bits.
|
||||||
input logic [`PA_BITS-1:0] MemPAdrM, // physical address
|
input logic [`PA_BITS-1:0] MemPAdrM, // physical address
|
||||||
input logic [11:0] VAdr, // when hptw writes dtlb we use this address to index SRAM.
|
|
||||||
|
input logic [`XLEN-1:0] FinalWriteDataM,
|
||||||
|
output logic [`XLEN-1:0] ReadDataWordM,
|
||||||
|
output logic DCacheStall,
|
||||||
|
output logic DCacheMiss,
|
||||||
|
output logic DCacheAccess,
|
||||||
|
|
||||||
|
output logic DCWriteLine,
|
||||||
|
output logic DCFetchLine,
|
||||||
|
input logic BUSACK,
|
||||||
|
|
||||||
|
|
||||||
|
output logic [`PA_BITS-1:0] BasePAdrM,
|
||||||
|
output logic [`XLEN-1:0] ReadDataBlockSetsM [(`DCACHE_BLOCKLENINBITS/`XLEN)-1:0],
|
||||||
|
|
||||||
|
output logic SelFlush,
|
||||||
|
|
||||||
|
input logic [`DCACHE_BLOCKLENINBITS-1:0] DCacheMemWriteData,
|
||||||
|
|
||||||
input logic [`XLEN-1:0] WriteDataM,
|
|
||||||
output logic [`XLEN-1:0] ReadDataM,
|
|
||||||
output logic DCacheStall,
|
|
||||||
output logic CommittedM,
|
|
||||||
output logic DCacheMiss,
|
|
||||||
output logic DCacheAccess,
|
|
||||||
|
|
||||||
// inputs from TLB and PMA/P
|
// inputs from TLB and PMA/P
|
||||||
input logic ExceptionM,
|
input logic CacheableM,
|
||||||
input logic PendingInterruptM,
|
|
||||||
input logic CacheableM,
|
|
||||||
// from ptw
|
// from ptw
|
||||||
input logic IgnoreRequest,
|
input logic IgnoreRequest
|
||||||
// ahb side
|
|
||||||
(* mark_debug = "true" *)output logic [`PA_BITS-1:0] AHBPAdr, // to ahb
|
|
||||||
(* mark_debug = "true" *)output logic AHBRead,
|
|
||||||
(* mark_debug = "true" *)output logic AHBWrite,
|
|
||||||
(* mark_debug = "true" *)input logic AHBAck, // from ahb
|
|
||||||
(* mark_debug = "true" *)input logic [`XLEN-1:0] HRDATA, // from ahb
|
|
||||||
(* mark_debug = "true" *)output logic [`XLEN-1:0] HWDATA, // to ahb
|
|
||||||
(* mark_debug = "true" *)output logic [2:0] DCtoAHBSizeM
|
|
||||||
);
|
);
|
||||||
|
|
||||||
localparam integer BLOCKLEN = `DCACHE_BLOCKLENINBITS;
|
localparam integer BLOCKLEN = `DCACHE_BLOCKLENINBITS;
|
||||||
@ -75,24 +76,19 @@ module dcache
|
|||||||
localparam integer LOGWPL = $clog2(WORDSPERLINE);
|
localparam integer LOGWPL = $clog2(WORDSPERLINE);
|
||||||
localparam integer LOGXLENBYTES = $clog2(`XLEN/8);
|
localparam integer LOGXLENBYTES = $clog2(`XLEN/8);
|
||||||
|
|
||||||
localparam integer FetchCountThreshold = WORDSPERLINE - 1;
|
|
||||||
localparam integer FlushAdrThreshold = NUMLINES - 1;
|
localparam integer FlushAdrThreshold = NUMLINES - 1;
|
||||||
|
|
||||||
logic [1:0] SelAdrM;
|
logic [1:0] SelAdrM;
|
||||||
logic [INDEXLEN-1:0] RAdr;
|
logic [INDEXLEN-1:0] RAdr;
|
||||||
logic [INDEXLEN-1:0] WAdr;
|
logic [INDEXLEN-1:0] WAdr;
|
||||||
logic [BLOCKLEN-1:0] SRAMWriteData;
|
logic [BLOCKLEN-1:0] SRAMWriteData;
|
||||||
logic [BLOCKLEN-1:0] DCacheMemWriteData;
|
|
||||||
logic SetValid, ClearValid;
|
logic SetValid, ClearValid;
|
||||||
logic SetDirty, ClearDirty;
|
logic SetDirty, ClearDirty;
|
||||||
logic [BLOCKLEN-1:0] ReadDataBlockWayMaskedM [NUMWAYS-1:0];
|
logic [BLOCKLEN-1:0] ReadDataBlockWayMaskedM [NUMWAYS-1:0];
|
||||||
logic [NUMWAYS-1:0] WayHit;
|
logic [NUMWAYS-1:0] WayHit;
|
||||||
logic CacheHit;
|
logic CacheHit;
|
||||||
logic [BLOCKLEN-1:0] ReadDataBlockM;
|
logic [BLOCKLEN-1:0] ReadDataBlockM;
|
||||||
logic [`XLEN-1:0] ReadDataBlockSetsM [(WORDSPERLINE)-1:0];
|
logic [`XLEN-1:0] ReadDataWordMuxM;
|
||||||
logic [`XLEN-1:0] ReadDataWordM, ReadDataWordMuxM;
|
|
||||||
logic [`XLEN-1:0] FinalWriteDataM, FinalAMOWriteDataM;
|
|
||||||
logic [LOGWPL-1:0] FetchCount, NextFetchCount;
|
|
||||||
logic [WORDSPERLINE-1:0] SRAMWordEnable;
|
logic [WORDSPERLINE-1:0] SRAMWordEnable;
|
||||||
|
|
||||||
logic SRAMWordWriteEnableM;
|
logic SRAMWordWriteEnableM;
|
||||||
@ -105,12 +101,9 @@ module dcache
|
|||||||
logic [NUMWAYS-1:0] VictimWay;
|
logic [NUMWAYS-1:0] VictimWay;
|
||||||
logic [NUMWAYS-1:0] VictimDirtyWay;
|
logic [NUMWAYS-1:0] VictimDirtyWay;
|
||||||
logic VictimDirty;
|
logic VictimDirty;
|
||||||
logic SelUncached;
|
|
||||||
logic [2**LOGWPL-1:0] MemPAdrDecodedW;
|
logic [2**LOGWPL-1:0] MemPAdrDecodedW;
|
||||||
|
|
||||||
logic [`PA_BITS-1:0] BasePAdrM;
|
|
||||||
logic [OFFSETLEN-1:0] BasePAdrOffsetM;
|
|
||||||
logic [`PA_BITS-1:0] BasePAdrMaskedM;
|
|
||||||
logic [TAGLEN-1:0] VictimTagWay [NUMWAYS-1:0];
|
logic [TAGLEN-1:0] VictimTagWay [NUMWAYS-1:0];
|
||||||
logic [TAGLEN-1:0] VictimTag;
|
logic [TAGLEN-1:0] VictimTag;
|
||||||
|
|
||||||
@ -125,12 +118,8 @@ module dcache
|
|||||||
logic FlushWayCntEn;
|
logic FlushWayCntEn;
|
||||||
logic FlushWayCntRst;
|
logic FlushWayCntRst;
|
||||||
|
|
||||||
logic SelFlush;
|
|
||||||
logic VDWriteEnable;
|
logic VDWriteEnable;
|
||||||
|
|
||||||
logic FetchCountFlag;
|
|
||||||
logic CntEn;
|
|
||||||
logic CntReset;
|
|
||||||
logic SelEvict;
|
logic SelEvict;
|
||||||
|
|
||||||
logic LRUWriteEn;
|
logic LRUWriteEn;
|
||||||
@ -141,9 +130,8 @@ module dcache
|
|||||||
|
|
||||||
mux4 #(INDEXLEN)
|
mux4 #(INDEXLEN)
|
||||||
AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||||
.d1(VAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), // *** REMOVE
|
.d1(7'b0), // *** REMOVE
|
||||||
.d2(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
.d2(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||||
//.d2(VAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
|
||||||
.d3(FlushAdr),
|
.d3(FlushAdr),
|
||||||
.s(SelAdrM),
|
.s(SelAdrM),
|
||||||
.y(RAdr));
|
.y(RAdr));
|
||||||
@ -220,16 +208,6 @@ module dcache
|
|||||||
|
|
||||||
assign ReadDataWordM = ReadDataBlockSetsM[MemPAdrM[$clog2(WORDSPERLINE+`XLEN/8) : $clog2(`XLEN/8)]];
|
assign ReadDataWordM = ReadDataBlockSetsM[MemPAdrM[$clog2(WORDSPERLINE+`XLEN/8) : $clog2(`XLEN/8)]];
|
||||||
|
|
||||||
mux2 #(`XLEN) UnCachedDataMux(.d0(ReadDataWordM),
|
|
||||||
.d1(DCacheMemWriteData[`XLEN-1:0]),
|
|
||||||
.s(SelUncached),
|
|
||||||
.y(ReadDataWordMuxM));
|
|
||||||
|
|
||||||
// finally swr
|
|
||||||
subwordread subwordread(.ReadDataWordMuxM,
|
|
||||||
.MemPAdrM(MemPAdrM[2:0]),
|
|
||||||
.Funct3M,
|
|
||||||
.ReadDataM);
|
|
||||||
|
|
||||||
// Write Path CPU (IEU) side
|
// Write Path CPU (IEU) side
|
||||||
|
|
||||||
@ -246,21 +224,6 @@ module dcache
|
|||||||
.s(SRAMBlockWriteEnableM),
|
.s(SRAMBlockWriteEnableM),
|
||||||
.y(SRAMWayWriteEnable));
|
.y(SRAMWayWriteEnable));
|
||||||
|
|
||||||
generate
|
|
||||||
if (`A_SUPPORTED) begin
|
|
||||||
logic [`XLEN-1:0] AMOResult;
|
|
||||||
amoalu amoalu(.srca(ReadDataM), .srcb(WriteDataM), .funct(Funct7M), .width(Funct3M[1:0]),
|
|
||||||
.result(AMOResult));
|
|
||||||
mux2 #(`XLEN) wdmux(WriteDataM, AMOResult, AtomicM[1], FinalAMOWriteDataM);
|
|
||||||
end else
|
|
||||||
assign FinalAMOWriteDataM = WriteDataM;
|
|
||||||
endgenerate
|
|
||||||
|
|
||||||
subwordwrite subwordwrite(.HRDATA(ReadDataWordM),
|
|
||||||
.HADDRD(MemPAdrM[2:0]),
|
|
||||||
.HSIZED({Funct3M[2], 1'b0, Funct3M[1:0]}),
|
|
||||||
.HWDATAIN(FinalAMOWriteDataM),
|
|
||||||
.HWDATA(FinalWriteDataM));
|
|
||||||
|
|
||||||
|
|
||||||
mux2 #(BLOCKLEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteDataM}}),
|
mux2 #(BLOCKLEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteDataM}}),
|
||||||
@ -268,44 +231,13 @@ module dcache
|
|||||||
.s(SRAMBlockWriteEnableM),
|
.s(SRAMBlockWriteEnableM),
|
||||||
.y(SRAMWriteData));
|
.y(SRAMWriteData));
|
||||||
|
|
||||||
// Bus Side logic
|
|
||||||
// register the fetch data from the next level of memory.
|
|
||||||
// This register should be necessary for timing. There is no register in the uncore or
|
|
||||||
// ahblite controller between the memories and this cache.
|
|
||||||
generate
|
|
||||||
for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
|
|
||||||
flopen #(`XLEN) fb(.clk(clk),
|
|
||||||
.en(AHBAck & AHBRead & (index == FetchCount)),
|
|
||||||
.d(HRDATA),
|
|
||||||
.q(DCacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN]));
|
|
||||||
end
|
|
||||||
endgenerate
|
|
||||||
|
|
||||||
mux3 #(`PA_BITS) BaseAdrMux(.d0(MemPAdrM),
|
mux3 #(`PA_BITS) BaseAdrMux(.d0(MemPAdrM),
|
||||||
.d1({VictimTag, MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
|
.d1({VictimTag, MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
|
||||||
.d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}),
|
.d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}),
|
||||||
.s({SelFlush, SelEvict}),
|
.s({SelFlush, SelEvict}),
|
||||||
.y(BasePAdrM));
|
.y(BasePAdrM));
|
||||||
|
|
||||||
// if not cacheable the offset bits needs to be sent to the EBU.
|
|
||||||
// if cacheable the offset bits are discarded. $ FSM will fetch the whole block.
|
|
||||||
assign BasePAdrOffsetM = CacheableM ? {{OFFSETLEN}{1'b0}} : BasePAdrM[OFFSETLEN-1:0];
|
|
||||||
assign BasePAdrMaskedM = {BasePAdrM[`PA_BITS-1:OFFSETLEN], BasePAdrOffsetM};
|
|
||||||
|
|
||||||
assign AHBPAdr = ({{`PA_BITS-LOGWPL{1'b0}}, FetchCount} << $clog2(`XLEN/8)) + BasePAdrMaskedM;
|
|
||||||
|
|
||||||
assign HWDATA = CacheableM | SelFlush ? ReadDataBlockSetsM[FetchCount] : WriteDataM;
|
|
||||||
|
|
||||||
assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL-1:0]);
|
|
||||||
|
|
||||||
flopenr #(LOGWPL)
|
|
||||||
FetchCountReg(.clk(clk),
|
|
||||||
.reset(reset | CntReset),
|
|
||||||
.en(CntEn),
|
|
||||||
.d(NextFetchCount),
|
|
||||||
.q(FetchCount));
|
|
||||||
|
|
||||||
assign NextFetchCount = FetchCount + 1'b1;
|
|
||||||
|
|
||||||
// flush address and way generation.
|
// flush address and way generation.
|
||||||
flopenr #(INDEXLEN)
|
flopenr #(INDEXLEN)
|
||||||
@ -331,10 +263,6 @@ module dcache
|
|||||||
|
|
||||||
assign FlushAdrFlag = FlushAdr == FlushAdrThreshold[INDEXLEN-1:0] & FlushWay[NUMWAYS-1];
|
assign FlushAdrFlag = FlushAdr == FlushAdrThreshold[INDEXLEN-1:0] & FlushWay[NUMWAYS-1];
|
||||||
|
|
||||||
generate
|
|
||||||
if (`XLEN == 32) assign DCtoAHBSizeM = CacheableM | SelFlush ? 3'b010 : Funct3M;
|
|
||||||
else assign DCtoAHBSizeM = CacheableM | SelFlush ? 3'b011 : Funct3M;
|
|
||||||
endgenerate;
|
|
||||||
|
|
||||||
//assign SRAMWriteEnable = SRAMBlockWriteEnableM | SRAMWordWriteEnableM;
|
//assign SRAMWriteEnable = SRAMBlockWriteEnableM | SRAMWordWriteEnableM;
|
||||||
|
|
||||||
@ -342,33 +270,26 @@ module dcache
|
|||||||
|
|
||||||
dcachefsm dcachefsm(.clk,
|
dcachefsm dcachefsm(.clk,
|
||||||
.reset,
|
.reset,
|
||||||
|
.DCFetchLine,
|
||||||
|
.DCWriteLine,
|
||||||
|
.BUSACK,
|
||||||
.MemRWM,
|
.MemRWM,
|
||||||
.AtomicM,
|
.AtomicM,
|
||||||
.ExceptionM,
|
|
||||||
.PendingInterruptM,
|
|
||||||
.CPUBusy,
|
.CPUBusy,
|
||||||
.CacheableM,
|
.CacheableM,
|
||||||
.IgnoreRequest,
|
.IgnoreRequest,
|
||||||
.AHBAck, // from ahb
|
|
||||||
.CacheHit,
|
.CacheHit,
|
||||||
.FetchCountFlag,
|
|
||||||
.VictimDirty,
|
.VictimDirty,
|
||||||
.DCacheStall,
|
.DCacheStall,
|
||||||
.CommittedM,
|
|
||||||
.DCacheMiss,
|
.DCacheMiss,
|
||||||
.DCacheAccess,
|
.DCacheAccess,
|
||||||
.AHBRead,
|
|
||||||
.AHBWrite,
|
|
||||||
.SelAdrM,
|
.SelAdrM,
|
||||||
.CntEn,
|
|
||||||
.SetValid,
|
.SetValid,
|
||||||
.ClearValid,
|
.ClearValid,
|
||||||
.SetDirty,
|
.SetDirty,
|
||||||
.ClearDirty,
|
.ClearDirty,
|
||||||
.SRAMWordWriteEnableM,
|
.SRAMWordWriteEnableM,
|
||||||
.SRAMBlockWriteEnableM,
|
.SRAMBlockWriteEnableM,
|
||||||
.CntReset,
|
|
||||||
.SelUncached,
|
|
||||||
.SelEvict,
|
.SelEvict,
|
||||||
.SelFlush,
|
.SelFlush,
|
||||||
.FlushAdrCntEn,
|
.FlushAdrCntEn,
|
||||||
|
|||||||
124
wally-pipelined/src/cache/dcachefsm.sv
vendored
124
wally-pipelined/src/cache/dcachefsm.sv
vendored
@ -33,41 +33,35 @@ module dcachefsm
|
|||||||
input logic [1:0] AtomicM,
|
input logic [1:0] AtomicM,
|
||||||
input logic FlushDCacheM,
|
input logic FlushDCacheM,
|
||||||
// hazard inputs
|
// hazard inputs
|
||||||
input logic ExceptionM,
|
|
||||||
input logic PendingInterruptM,
|
|
||||||
input logic CPUBusy,
|
input logic CPUBusy,
|
||||||
input logic CacheableM,
|
input logic CacheableM,
|
||||||
// hptw inputs
|
// hptw inputs
|
||||||
input logic IgnoreRequest,
|
input logic IgnoreRequest,
|
||||||
// Bus inputs
|
// Bus inputs
|
||||||
input logic AHBAck, // from ahb
|
input logic BUSACK,
|
||||||
// dcache internals
|
// dcache internals
|
||||||
input logic CacheHit,
|
input logic CacheHit,
|
||||||
input logic FetchCountFlag,
|
|
||||||
input logic VictimDirty,
|
input logic VictimDirty,
|
||||||
input logic FlushAdrFlag,
|
input logic FlushAdrFlag,
|
||||||
|
|
||||||
// hazard outputs
|
// hazard outputs
|
||||||
output logic DCacheStall,
|
output logic DCacheStall,
|
||||||
output logic CommittedM,
|
|
||||||
// counter outputs
|
// counter outputs
|
||||||
output logic DCacheMiss,
|
output logic DCacheMiss,
|
||||||
output logic DCacheAccess,
|
output logic DCacheAccess,
|
||||||
// Bus outputs
|
// Bus outputs
|
||||||
output logic AHBRead,
|
|
||||||
output logic AHBWrite,
|
output logic DCWriteLine,
|
||||||
|
output logic DCFetchLine,
|
||||||
|
|
||||||
// dcache internals
|
// dcache internals
|
||||||
output logic [1:0] SelAdrM,
|
output logic [1:0] SelAdrM,
|
||||||
output logic CntEn,
|
|
||||||
output logic SetValid,
|
output logic SetValid,
|
||||||
output logic ClearValid,
|
output logic ClearValid,
|
||||||
output logic SetDirty,
|
output logic SetDirty,
|
||||||
output logic ClearDirty,
|
output logic ClearDirty,
|
||||||
output logic SRAMWordWriteEnableM,
|
output logic SRAMWordWriteEnableM,
|
||||||
output logic SRAMBlockWriteEnableM,
|
output logic SRAMBlockWriteEnableM,
|
||||||
output logic CntReset,
|
|
||||||
output logic SelUncached,
|
|
||||||
output logic SelEvict,
|
output logic SelEvict,
|
||||||
output logic LRUWriteEn,
|
output logic LRUWriteEn,
|
||||||
output logic SelFlush,
|
output logic SelFlush,
|
||||||
@ -79,7 +73,6 @@ module dcachefsm
|
|||||||
|
|
||||||
);
|
);
|
||||||
|
|
||||||
logic PreCntEn;
|
|
||||||
logic AnyCPUReqM;
|
logic AnyCPUReqM;
|
||||||
|
|
||||||
typedef enum {STATE_READY,
|
typedef enum {STATE_READY,
|
||||||
@ -92,11 +85,6 @@ module dcachefsm
|
|||||||
STATE_MISS_READ_WORD_DELAY,
|
STATE_MISS_READ_WORD_DELAY,
|
||||||
STATE_MISS_WRITE_WORD,
|
STATE_MISS_WRITE_WORD,
|
||||||
|
|
||||||
STATE_UNCACHED_WRITE,
|
|
||||||
STATE_UNCACHED_WRITE_DONE,
|
|
||||||
STATE_UNCACHED_READ,
|
|
||||||
STATE_UNCACHED_READ_DONE,
|
|
||||||
|
|
||||||
STATE_CPU_BUSY,
|
STATE_CPU_BUSY,
|
||||||
STATE_CPU_BUSY_FINISH_AMO,
|
STATE_CPU_BUSY_FINISH_AMO,
|
||||||
|
|
||||||
@ -107,7 +95,6 @@ module dcachefsm
|
|||||||
(* mark_debug = "true" *) statetype CurrState, NextState;
|
(* mark_debug = "true" *) statetype CurrState, NextState;
|
||||||
|
|
||||||
assign AnyCPUReqM = |MemRWM | (|AtomicM);
|
assign AnyCPUReqM = |MemRWM | (|AtomicM);
|
||||||
assign CntEn = PreCntEn & AHBAck;
|
|
||||||
|
|
||||||
// outputs for the performance counters.
|
// outputs for the performance counters.
|
||||||
assign DCacheAccess = AnyCPUReqM & CacheableM & CurrState == STATE_READY;
|
assign DCacheAccess = AnyCPUReqM & CacheableM & CurrState == STATE_READY;
|
||||||
@ -121,18 +108,12 @@ module dcachefsm
|
|||||||
always_comb begin
|
always_comb begin
|
||||||
DCacheStall = 1'b0;
|
DCacheStall = 1'b0;
|
||||||
SelAdrM = 2'b00;
|
SelAdrM = 2'b00;
|
||||||
PreCntEn = 1'b0;
|
|
||||||
SetValid = 1'b0;
|
SetValid = 1'b0;
|
||||||
ClearValid = 1'b0;
|
ClearValid = 1'b0;
|
||||||
SetDirty = 1'b0;
|
SetDirty = 1'b0;
|
||||||
ClearDirty = 1'b0;
|
ClearDirty = 1'b0;
|
||||||
SRAMWordWriteEnableM = 1'b0;
|
SRAMWordWriteEnableM = 1'b0;
|
||||||
SRAMBlockWriteEnableM = 1'b0;
|
SRAMBlockWriteEnableM = 1'b0;
|
||||||
CntReset = 1'b0;
|
|
||||||
AHBRead = 1'b0;
|
|
||||||
AHBWrite = 1'b0;
|
|
||||||
CommittedM = 1'b0;
|
|
||||||
SelUncached = 1'b0;
|
|
||||||
SelEvict = 1'b0;
|
SelEvict = 1'b0;
|
||||||
LRUWriteEn = 1'b0;
|
LRUWriteEn = 1'b0;
|
||||||
SelFlush = 1'b0;
|
SelFlush = 1'b0;
|
||||||
@ -142,19 +123,17 @@ module dcachefsm
|
|||||||
FlushWayCntRst = 1'b0;
|
FlushWayCntRst = 1'b0;
|
||||||
VDWriteEnable = 1'b0;
|
VDWriteEnable = 1'b0;
|
||||||
NextState = STATE_READY;
|
NextState = STATE_READY;
|
||||||
|
DCFetchLine = 1'b0;
|
||||||
|
DCWriteLine = 1'b0;
|
||||||
|
|
||||||
case (CurrState)
|
case (CurrState)
|
||||||
STATE_READY: begin
|
STATE_READY: begin
|
||||||
|
|
||||||
CntReset = 1'b0;
|
|
||||||
DCacheStall = 1'b0;
|
DCacheStall = 1'b0;
|
||||||
AHBRead = 1'b0;
|
|
||||||
AHBWrite = 1'b0;
|
|
||||||
SelAdrM = 2'b00;
|
SelAdrM = 2'b00;
|
||||||
SRAMWordWriteEnableM = 1'b0;
|
SRAMWordWriteEnableM = 1'b0;
|
||||||
SetDirty = 1'b0;
|
SetDirty = 1'b0;
|
||||||
LRUWriteEn = 1'b0;
|
LRUWriteEn = 1'b0;
|
||||||
CommittedM = 1'b0;
|
|
||||||
|
|
||||||
// TLB Miss
|
// TLB Miss
|
||||||
if(IgnoreRequest) begin
|
if(IgnoreRequest) begin
|
||||||
@ -164,7 +143,6 @@ module dcachefsm
|
|||||||
// PTW ready the CPU will stall.
|
// PTW ready the CPU will stall.
|
||||||
// The page table walker asserts it's control 1 cycle
|
// The page table walker asserts it's control 1 cycle
|
||||||
// after the TLBs miss.
|
// after the TLBs miss.
|
||||||
// CommittedM = 1'b1; ??? *** Not Sure yet.
|
|
||||||
NextState = STATE_READY;
|
NextState = STATE_READY;
|
||||||
end
|
end
|
||||||
|
|
||||||
@ -225,34 +203,17 @@ module dcachefsm
|
|||||||
// read or write miss valid cached
|
// read or write miss valid cached
|
||||||
else if((|MemRWM) & CacheableM & ~CacheHit) begin
|
else if((|MemRWM) & CacheableM & ~CacheHit) begin
|
||||||
NextState = STATE_MISS_FETCH_WDV;
|
NextState = STATE_MISS_FETCH_WDV;
|
||||||
CntReset = 1'b1;
|
|
||||||
DCacheStall = 1'b1;
|
DCacheStall = 1'b1;
|
||||||
end
|
DCFetchLine = 1'b1;
|
||||||
// uncached write
|
|
||||||
else if(MemRWM[0] & ~CacheableM) begin
|
|
||||||
NextState = STATE_UNCACHED_WRITE;
|
|
||||||
CntReset = 1'b1;
|
|
||||||
DCacheStall = 1'b1;
|
|
||||||
AHBWrite = 1'b1;
|
|
||||||
end
|
|
||||||
// uncached read
|
|
||||||
else if(MemRWM[1] & ~CacheableM) begin
|
|
||||||
NextState = STATE_UNCACHED_READ;
|
|
||||||
CntReset = 1'b1;
|
|
||||||
DCacheStall = 1'b1;
|
|
||||||
AHBRead = 1'b1;
|
|
||||||
end
|
end
|
||||||
else NextState = STATE_READY;
|
else NextState = STATE_READY;
|
||||||
end
|
end
|
||||||
|
|
||||||
STATE_MISS_FETCH_WDV: begin
|
STATE_MISS_FETCH_WDV: begin
|
||||||
DCacheStall = 1'b1;
|
DCacheStall = 1'b1;
|
||||||
PreCntEn = 1'b1;
|
|
||||||
AHBRead = 1'b1;
|
|
||||||
SelAdrM = 2'b10;
|
SelAdrM = 2'b10;
|
||||||
CommittedM = 1'b1;
|
|
||||||
|
|
||||||
if (FetchCountFlag & AHBAck) begin
|
if (BUSACK) begin
|
||||||
NextState = STATE_MISS_FETCH_DONE;
|
NextState = STATE_MISS_FETCH_DONE;
|
||||||
end else begin
|
end else begin
|
||||||
NextState = STATE_MISS_FETCH_WDV;
|
NextState = STATE_MISS_FETCH_WDV;
|
||||||
@ -262,10 +223,9 @@ module dcachefsm
|
|||||||
STATE_MISS_FETCH_DONE: begin
|
STATE_MISS_FETCH_DONE: begin
|
||||||
DCacheStall = 1'b1;
|
DCacheStall = 1'b1;
|
||||||
SelAdrM = 2'b10;
|
SelAdrM = 2'b10;
|
||||||
CntReset = 1'b1;
|
|
||||||
CommittedM = 1'b1;
|
|
||||||
if(VictimDirty) begin
|
if(VictimDirty) begin
|
||||||
NextState = STATE_MISS_EVICT_DIRTY;
|
NextState = STATE_MISS_EVICT_DIRTY;
|
||||||
|
DCWriteLine = 1'b1;
|
||||||
end else begin
|
end else begin
|
||||||
NextState = STATE_MISS_WRITE_CACHE_BLOCK;
|
NextState = STATE_MISS_WRITE_CACHE_BLOCK;
|
||||||
end
|
end
|
||||||
@ -278,14 +238,12 @@ module dcachefsm
|
|||||||
SelAdrM = 2'b10;
|
SelAdrM = 2'b10;
|
||||||
SetValid = 1'b1;
|
SetValid = 1'b1;
|
||||||
ClearDirty = 1'b1;
|
ClearDirty = 1'b1;
|
||||||
CommittedM = 1'b1;
|
|
||||||
//LRUWriteEn = 1'b1; // DO not update LRU on SRAM fetch update. Wait for subsequent read/write
|
//LRUWriteEn = 1'b1; // DO not update LRU on SRAM fetch update. Wait for subsequent read/write
|
||||||
end
|
end
|
||||||
|
|
||||||
STATE_MISS_READ_WORD: begin
|
STATE_MISS_READ_WORD: begin
|
||||||
SelAdrM = 2'b10;
|
SelAdrM = 2'b10;
|
||||||
DCacheStall = 1'b1;
|
DCacheStall = 1'b1;
|
||||||
CommittedM = 1'b1;
|
|
||||||
if (MemRWM[0] & ~AtomicM[1]) begin // handles stores and amo write.
|
if (MemRWM[0] & ~AtomicM[1]) begin // handles stores and amo write.
|
||||||
NextState = STATE_MISS_WRITE_WORD;
|
NextState = STATE_MISS_WRITE_WORD;
|
||||||
end else begin
|
end else begin
|
||||||
@ -297,7 +255,6 @@ module dcachefsm
|
|||||||
|
|
||||||
STATE_MISS_READ_WORD_DELAY: begin
|
STATE_MISS_READ_WORD_DELAY: begin
|
||||||
//SelAdrM = 2'b10;
|
//SelAdrM = 2'b10;
|
||||||
CommittedM = 1'b1;
|
|
||||||
SRAMWordWriteEnableM = 1'b0;
|
SRAMWordWriteEnableM = 1'b0;
|
||||||
SetDirty = 1'b0;
|
SetDirty = 1'b0;
|
||||||
LRUWriteEn = 1'b0;
|
LRUWriteEn = 1'b0;
|
||||||
@ -328,7 +285,6 @@ module dcachefsm
|
|||||||
SRAMWordWriteEnableM = 1'b1;
|
SRAMWordWriteEnableM = 1'b1;
|
||||||
SetDirty = 1'b1;
|
SetDirty = 1'b1;
|
||||||
SelAdrM = 2'b10;
|
SelAdrM = 2'b10;
|
||||||
CommittedM = 1'b1;
|
|
||||||
LRUWriteEn = 1'b1;
|
LRUWriteEn = 1'b1;
|
||||||
if(CPUBusy) begin
|
if(CPUBusy) begin
|
||||||
NextState = STATE_CPU_BUSY;
|
NextState = STATE_CPU_BUSY;
|
||||||
@ -341,12 +297,9 @@ module dcachefsm
|
|||||||
|
|
||||||
STATE_MISS_EVICT_DIRTY: begin
|
STATE_MISS_EVICT_DIRTY: begin
|
||||||
DCacheStall = 1'b1;
|
DCacheStall = 1'b1;
|
||||||
PreCntEn = 1'b1;
|
|
||||||
AHBWrite = 1'b1;
|
|
||||||
SelAdrM = 2'b10;
|
SelAdrM = 2'b10;
|
||||||
CommittedM = 1'b1;
|
|
||||||
SelEvict = 1'b1;
|
SelEvict = 1'b1;
|
||||||
if(FetchCountFlag & AHBAck) begin
|
if(BUSACK) begin
|
||||||
NextState = STATE_MISS_WRITE_CACHE_BLOCK;
|
NextState = STATE_MISS_WRITE_CACHE_BLOCK;
|
||||||
end else begin
|
end else begin
|
||||||
NextState = STATE_MISS_EVICT_DIRTY;
|
NextState = STATE_MISS_EVICT_DIRTY;
|
||||||
@ -355,7 +308,6 @@ module dcachefsm
|
|||||||
|
|
||||||
|
|
||||||
STATE_CPU_BUSY: begin
|
STATE_CPU_BUSY: begin
|
||||||
CommittedM = 1'b1;
|
|
||||||
SelAdrM = 2'b00;
|
SelAdrM = 2'b00;
|
||||||
if(CPUBusy) begin
|
if(CPUBusy) begin
|
||||||
NextState = STATE_CPU_BUSY;
|
NextState = STATE_CPU_BUSY;
|
||||||
@ -367,7 +319,6 @@ module dcachefsm
|
|||||||
end
|
end
|
||||||
|
|
||||||
STATE_CPU_BUSY_FINISH_AMO: begin
|
STATE_CPU_BUSY_FINISH_AMO: begin
|
||||||
CommittedM = 1'b1;
|
|
||||||
SelAdrM = 2'b10;
|
SelAdrM = 2'b10;
|
||||||
SRAMWordWriteEnableM = 1'b0;
|
SRAMWordWriteEnableM = 1'b0;
|
||||||
SetDirty = 1'b0;
|
SetDirty = 1'b0;
|
||||||
@ -383,65 +334,17 @@ module dcachefsm
|
|||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
STATE_UNCACHED_WRITE : begin
|
|
||||||
DCacheStall = 1'b1;
|
|
||||||
AHBWrite = 1'b1;
|
|
||||||
CommittedM = 1'b1;
|
|
||||||
if(AHBAck) begin
|
|
||||||
NextState = STATE_UNCACHED_WRITE_DONE;
|
|
||||||
end else begin
|
|
||||||
NextState = STATE_UNCACHED_WRITE;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
STATE_UNCACHED_READ: begin
|
|
||||||
DCacheStall = 1'b1;
|
|
||||||
AHBRead = 1'b1;
|
|
||||||
CommittedM = 1'b1;
|
|
||||||
if(AHBAck) begin
|
|
||||||
NextState = STATE_UNCACHED_READ_DONE;
|
|
||||||
end else begin
|
|
||||||
NextState = STATE_UNCACHED_READ;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
STATE_UNCACHED_WRITE_DONE: begin
|
|
||||||
CommittedM = 1'b1;
|
|
||||||
SelAdrM = 2'b00;
|
|
||||||
if(CPUBusy) begin
|
|
||||||
NextState = STATE_CPU_BUSY;
|
|
||||||
SelAdrM = 2'b10;
|
|
||||||
end
|
|
||||||
else begin
|
|
||||||
NextState = STATE_READY;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
STATE_UNCACHED_READ_DONE: begin
|
|
||||||
CommittedM = 1'b1;
|
|
||||||
SelUncached = 1'b1;
|
|
||||||
SelAdrM = 2'b00;
|
|
||||||
if(CPUBusy) begin
|
|
||||||
NextState = STATE_CPU_BUSY;
|
|
||||||
SelAdrM = 2'b10;
|
|
||||||
end
|
|
||||||
else begin
|
|
||||||
NextState = STATE_READY;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
STATE_FLUSH: begin
|
STATE_FLUSH: begin
|
||||||
DCacheStall = 1'b1;
|
DCacheStall = 1'b1;
|
||||||
CommittedM = 1'b1;
|
|
||||||
SelAdrM = 2'b11;
|
SelAdrM = 2'b11;
|
||||||
SelFlush = 1'b1;
|
SelFlush = 1'b1;
|
||||||
FlushAdrCntEn = 1'b1;
|
FlushAdrCntEn = 1'b1;
|
||||||
FlushWayCntEn = 1'b1;
|
FlushWayCntEn = 1'b1;
|
||||||
CntReset = 1'b1;
|
|
||||||
if(VictimDirty) begin
|
if(VictimDirty) begin
|
||||||
NextState = STATE_FLUSH_WRITE_BACK;
|
NextState = STATE_FLUSH_WRITE_BACK;
|
||||||
FlushAdrCntEn = 1'b0;
|
FlushAdrCntEn = 1'b0;
|
||||||
FlushWayCntEn = 1'b0;
|
FlushWayCntEn = 1'b0;
|
||||||
|
DCWriteLine = 1'b1;
|
||||||
end else if (FlushAdrFlag) begin
|
end else if (FlushAdrFlag) begin
|
||||||
NextState = STATE_READY;
|
NextState = STATE_READY;
|
||||||
DCacheStall = 1'b0;
|
DCacheStall = 1'b0;
|
||||||
@ -454,12 +357,9 @@ module dcachefsm
|
|||||||
|
|
||||||
STATE_FLUSH_WRITE_BACK: begin
|
STATE_FLUSH_WRITE_BACK: begin
|
||||||
DCacheStall = 1'b1;
|
DCacheStall = 1'b1;
|
||||||
AHBWrite = 1'b1;
|
|
||||||
SelAdrM = 2'b11;
|
SelAdrM = 2'b11;
|
||||||
CommittedM = 1'b1;
|
|
||||||
SelFlush = 1'b1;
|
SelFlush = 1'b1;
|
||||||
PreCntEn = 1'b1;
|
if(BUSACK) begin
|
||||||
if(FetchCountFlag & AHBAck) begin
|
|
||||||
NextState = STATE_FLUSH_CLEAR_DIRTY;
|
NextState = STATE_FLUSH_CLEAR_DIRTY;
|
||||||
end else begin
|
end else begin
|
||||||
NextState = STATE_FLUSH_WRITE_BACK;
|
NextState = STATE_FLUSH_WRITE_BACK;
|
||||||
|
|||||||
2
wally-pipelined/src/cache/icache.sv
vendored
2
wally-pipelined/src/cache/icache.sv
vendored
@ -48,7 +48,6 @@ module icache
|
|||||||
output logic ICacheStallF,
|
output logic ICacheStallF,
|
||||||
input logic ITLBMissF,
|
input logic ITLBMissF,
|
||||||
input logic ITLBWriteF,
|
input logic ITLBWriteF,
|
||||||
input logic WalkerInstrPageFaultF,
|
|
||||||
input logic InvalidateICacheM,
|
input logic InvalidateICacheM,
|
||||||
|
|
||||||
// The raw (not decompressed) instruction that was requested
|
// The raw (not decompressed) instruction that was requested
|
||||||
@ -289,7 +288,6 @@ module icache
|
|||||||
.ICacheStallF,
|
.ICacheStallF,
|
||||||
.ITLBMissF,
|
.ITLBMissF,
|
||||||
.ITLBWriteF,
|
.ITLBWriteF,
|
||||||
.WalkerInstrPageFaultF,
|
|
||||||
.ExceptionM,
|
.ExceptionM,
|
||||||
.PendingInterruptM,
|
.PendingInterruptM,
|
||||||
.InstrAckF,
|
.InstrAckF,
|
||||||
|
|||||||
29
wally-pipelined/src/cache/icachefsm.sv
vendored
29
wally-pipelined/src/cache/icachefsm.sv
vendored
@ -34,7 +34,6 @@ module icachefsm
|
|||||||
// inputs from mmu
|
// inputs from mmu
|
||||||
input logic ITLBMissF,
|
input logic ITLBMissF,
|
||||||
input logic ITLBWriteF,
|
input logic ITLBWriteF,
|
||||||
input logic WalkerInstrPageFaultF,
|
|
||||||
|
|
||||||
input logic ExceptionM, PendingInterruptM,
|
input logic ExceptionM, PendingInterruptM,
|
||||||
|
|
||||||
@ -334,31 +333,8 @@ module icachefsm
|
|||||||
NextState = STATE_READY;
|
NextState = STATE_READY;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
/* -----\/----- EXCLUDED -----\/-----
|
|
||||||
STATE_TLB_MISS: begin
|
|
||||||
if (WalkerInstrPageFaultF) begin
|
|
||||||
NextState = STATE_READY;
|
|
||||||
ICacheStallF = 1'b0;
|
|
||||||
end else if (ITLBWriteF) begin
|
|
||||||
NextState = STATE_TLB_MISS_DONE;
|
|
||||||
ICacheStallF = 1'b1;
|
|
||||||
end else begin
|
|
||||||
NextState = STATE_TLB_MISS;
|
|
||||||
ICacheStallF = 1'b0;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
STATE_TLB_MISS_DONE: begin
|
|
||||||
SelAdr = 2'b01;
|
|
||||||
NextState = STATE_READY;
|
|
||||||
end
|
|
||||||
-----/\----- EXCLUDED -----/\----- */
|
|
||||||
STATE_CPU_BUSY: begin
|
STATE_CPU_BUSY: begin
|
||||||
ICacheStallF = 1'b0;
|
ICacheStallF = 1'b0;
|
||||||
/* -----\/----- EXCLUDED -----\/-----
|
|
||||||
if (ITLBMissF) begin
|
|
||||||
NextState = STATE_TLB_MISS;
|
|
||||||
end else
|
|
||||||
-----/\----- EXCLUDED -----/\----- */
|
|
||||||
if(StallF) begin
|
if(StallF) begin
|
||||||
NextState = STATE_CPU_BUSY;
|
NextState = STATE_CPU_BUSY;
|
||||||
SelAdr = 2'b01;
|
SelAdr = 2'b01;
|
||||||
@ -370,11 +346,6 @@ module icachefsm
|
|||||||
STATE_CPU_BUSY_SPILL: begin
|
STATE_CPU_BUSY_SPILL: begin
|
||||||
ICacheStallF = 1'b0;
|
ICacheStallF = 1'b0;
|
||||||
ICacheReadEn = 1'b1;
|
ICacheReadEn = 1'b1;
|
||||||
/* -----\/----- EXCLUDED -----\/-----
|
|
||||||
if (ITLBMissF) begin
|
|
||||||
NextState = STATE_TLB_MISS;
|
|
||||||
end else
|
|
||||||
-----/\----- EXCLUDED -----/\----- */
|
|
||||||
if(StallF) begin
|
if(StallF) begin
|
||||||
NextState = STATE_CPU_BUSY_SPILL;
|
NextState = STATE_CPU_BUSY_SPILL;
|
||||||
SelAdr = 2'b10;
|
SelAdr = 2'b10;
|
||||||
|
|||||||
@ -45,13 +45,13 @@ module ahblite (
|
|||||||
output logic [`XLEN-1:0] InstrRData,
|
output logic [`XLEN-1:0] InstrRData,
|
||||||
output logic InstrAckF,
|
output logic InstrAckF,
|
||||||
// Signals from Data Cache
|
// Signals from Data Cache
|
||||||
input logic [`PA_BITS-1:0] DCtoAHBPAdrM,
|
input logic [`PA_BITS-1:0] LsuBusAdr,
|
||||||
input logic DCtoAHBReadM,
|
input logic LsuBusRead,
|
||||||
input logic DCtoAHBWriteM,
|
input logic LsuBusWrite,
|
||||||
input logic [`XLEN-1:0] DCtoAHBWriteData,
|
input logic [`XLEN-1:0] LsuBusHWDATA,
|
||||||
output logic [`XLEN-1:0] DCfromAHBReadData,
|
output logic [`XLEN-1:0] LsuBusHRDATA,
|
||||||
input logic [1:0] MemSizeM, // *** remove
|
input logic [2:0] LsuBusSize,
|
||||||
output logic DCfromAHBAck,
|
output logic LsuBusAck,
|
||||||
// AHB-Lite external signals
|
// AHB-Lite external signals
|
||||||
(* mark_debug = "true" *) input logic [`AHBW-1:0] HRDATA,
|
(* mark_debug = "true" *) input logic [`AHBW-1:0] HRDATA,
|
||||||
(* mark_debug = "true" *) input logic HREADY, HRESP,
|
(* mark_debug = "true" *) input logic HREADY, HRESP,
|
||||||
@ -98,8 +98,8 @@ module ahblite (
|
|||||||
// interface that might be used in place of the ahblite.
|
// interface that might be used in place of the ahblite.
|
||||||
always_comb
|
always_comb
|
||||||
case (BusState)
|
case (BusState)
|
||||||
IDLE: if (DCtoAHBReadM) NextBusState = MEMREAD; // Memory has priority over instructions
|
IDLE: if (LsuBusRead) NextBusState = MEMREAD; // Memory has priority over instructions
|
||||||
else if (DCtoAHBWriteM)NextBusState = MEMWRITE;
|
else if (LsuBusWrite)NextBusState = MEMWRITE;
|
||||||
else if (InstrReadF) NextBusState = INSTRREAD;
|
else if (InstrReadF) NextBusState = INSTRREAD;
|
||||||
else NextBusState = IDLE;
|
else NextBusState = IDLE;
|
||||||
MEMREAD: if (~HREADY) NextBusState = MEMREAD;
|
MEMREAD: if (~HREADY) NextBusState = MEMREAD;
|
||||||
@ -116,17 +116,17 @@ module ahblite (
|
|||||||
|
|
||||||
// bus outputs
|
// bus outputs
|
||||||
assign #1 GrantData = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE);
|
assign #1 GrantData = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE);
|
||||||
assign #1 AccessAddress = (GrantData) ? DCtoAHBPAdrM[31:0] : InstrPAdrF[31:0];
|
assign #1 AccessAddress = (GrantData) ? LsuBusAdr[31:0] : InstrPAdrF[31:0];
|
||||||
assign #1 HADDR = AccessAddress;
|
assign #1 HADDR = AccessAddress;
|
||||||
assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway
|
assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway
|
||||||
assign HSIZE = (GrantData) ? {1'b0, MemSizeM} : ISize;
|
assign HSIZE = (GrantData) ? {1'b0, LsuBusSize[1:0]} : ISize;
|
||||||
assign HBURST = 3'b000; // Single burst only supported; consider generalizing for cache fillsfH
|
assign HBURST = 3'b000; // Single burst only supported; consider generalizing for cache fillsfH
|
||||||
assign HPROT = 4'b0011; // not used; see Section 3.7
|
assign HPROT = 4'b0011; // not used; see Section 3.7
|
||||||
assign HTRANS = (NextBusState != IDLE) ? 2'b10 : 2'b00; // NONSEQ if reading or writing, IDLE otherwise
|
assign HTRANS = (NextBusState != IDLE) ? 2'b10 : 2'b00; // NONSEQ if reading or writing, IDLE otherwise
|
||||||
assign HMASTLOCK = 0; // no locking supported
|
assign HMASTLOCK = 0; // no locking supported
|
||||||
assign HWRITE = NextBusState == MEMWRITE;
|
assign HWRITE = NextBusState == MEMWRITE;
|
||||||
// delay write data by one cycle for
|
// delay write data by one cycle for
|
||||||
flop #(`XLEN) wdreg(HCLK, DCtoAHBWriteData, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
|
flop #(`XLEN) wdreg(HCLK, LsuBusHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
|
||||||
// delay signals for subword writes
|
// delay signals for subword writes
|
||||||
flop #(3) adrreg(HCLK, HADDR[2:0], HADDRD);
|
flop #(3) adrreg(HCLK, HADDR[2:0], HADDRD);
|
||||||
flop #(4) sizereg(HCLK, {UnsignedLoadM, HSIZE}, HSIZED);
|
flop #(4) sizereg(HCLK, {UnsignedLoadM, HSIZE}, HSIZED);
|
||||||
@ -137,8 +137,8 @@ module ahblite (
|
|||||||
|
|
||||||
|
|
||||||
assign InstrRData = HRDATA;
|
assign InstrRData = HRDATA;
|
||||||
assign DCfromAHBReadData = HRDATA;
|
assign LsuBusHRDATA = HRDATA;
|
||||||
assign InstrAckF = (BusState == INSTRREAD) && (NextBusState != INSTRREAD);
|
assign InstrAckF = (BusState == INSTRREAD) && (NextBusState != INSTRREAD);
|
||||||
assign DCfromAHBAck = (BusState == MEMREAD) && (NextBusState != MEMREAD) || (BusState == MEMWRITE) && (NextBusState != MEMWRITE);
|
assign LsuBusAck = (BusState == MEMREAD) && (NextBusState != MEMREAD) || (BusState == MEMWRITE) && (NextBusState != MEMWRITE);
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|||||||
@ -74,7 +74,6 @@ module ifu (
|
|||||||
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
|
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
|
||||||
input logic [1:0] STATUS_MPP,
|
input logic [1:0] STATUS_MPP,
|
||||||
input logic ITLBWriteF, ITLBFlushF,
|
input logic ITLBWriteF, ITLBFlushF,
|
||||||
input logic WalkerInstrPageFaultF,
|
|
||||||
|
|
||||||
output logic ITLBMissF,
|
output logic ITLBMissF,
|
||||||
|
|
||||||
@ -172,7 +171,6 @@ module ifu (
|
|||||||
.PCNextF(PCNextFPhys),
|
.PCNextF(PCNextFPhys),
|
||||||
.PCPF(PCPFmmu),
|
.PCPF(PCPFmmu),
|
||||||
.PCF,
|
.PCF,
|
||||||
.WalkerInstrPageFaultF,
|
|
||||||
.InvalidateICacheM);
|
.InvalidateICacheM);
|
||||||
|
|
||||||
flopenl #(32) AlignedInstrRawDFlop(clk, reset | reset_q, ~StallD, FlushD ? nop : FinalInstrRawF, nop, InstrRawD);
|
flopenl #(32) AlignedInstrRawDFlop(clk, reset | reset_q, ~StallD, FlushD ? nop : FinalInstrRawF, nop, InstrRawD);
|
||||||
|
|||||||
@ -31,36 +31,29 @@ module lrsc
|
|||||||
input logic clk, reset,
|
input logic clk, reset,
|
||||||
input logic FlushW, CPUBusy,
|
input logic FlushW, CPUBusy,
|
||||||
input logic MemReadM,
|
input logic MemReadM,
|
||||||
input logic [1:0] MemRWMtoLRSC,
|
input logic [1:0] LsuRWM,
|
||||||
output logic [1:0] MemRWMtoDCache,
|
output logic [1:0] DCRWM,
|
||||||
input logic [1:0] AtomicMtoDCache,
|
input logic [1:0] LsuAtomicM,
|
||||||
input logic [`PA_BITS-1:0] MemPAdrM, // from mmu to dcache
|
input logic [`PA_BITS-1:0] MemPAdrM, // from mmu to dcache
|
||||||
output logic SquashSCW
|
output logic SquashSCW
|
||||||
);
|
);
|
||||||
// Handle atomic load reserved / store conditional
|
// Handle atomic load reserved / store conditional
|
||||||
generate
|
logic [`PA_BITS-1:2] ReservationPAdrW;
|
||||||
if (`A_SUPPORTED) begin // atomic instructions supported
|
logic ReservationValidM, ReservationValidW;
|
||||||
logic [`PA_BITS-1:2] ReservationPAdrW;
|
logic lrM, scM, WriteAdrMatchM;
|
||||||
logic ReservationValidM, ReservationValidW;
|
logic SquashSCM;
|
||||||
logic lrM, scM, WriteAdrMatchM;
|
|
||||||
logic SquashSCM;
|
|
||||||
|
|
||||||
assign lrM = MemReadM && AtomicMtoDCache[0];
|
assign lrM = MemReadM && LsuAtomicM[0];
|
||||||
assign scM = MemRWMtoLRSC[0] && AtomicMtoDCache[0];
|
assign scM = LsuRWM[0] && LsuAtomicM[0];
|
||||||
assign WriteAdrMatchM = MemRWMtoLRSC[0] && (MemPAdrM[`PA_BITS-1:2] == ReservationPAdrW) && ReservationValidW;
|
assign WriteAdrMatchM = LsuRWM[0] && (MemPAdrM[`PA_BITS-1:2] == ReservationPAdrW) && ReservationValidW;
|
||||||
assign SquashSCM = scM && ~WriteAdrMatchM;
|
assign SquashSCM = scM && ~WriteAdrMatchM;
|
||||||
assign MemRWMtoDCache = SquashSCM ? 2'b00 : MemRWMtoLRSC;
|
assign DCRWM = SquashSCM ? 2'b00 : LsuRWM;
|
||||||
always_comb begin // ReservationValidM (next value of valid reservation)
|
always_comb begin // ReservationValidM (next value of valid reservation)
|
||||||
if (lrM) ReservationValidM = 1; // set valid on load reserve
|
if (lrM) ReservationValidM = 1; // set valid on load reserve
|
||||||
else if (scM || WriteAdrMatchM) ReservationValidM = 0; // clear valid on store to same address or any sc
|
else if (scM || WriteAdrMatchM) ReservationValidM = 0; // clear valid on store to same address or any sc
|
||||||
else ReservationValidM = ReservationValidW; // otherwise don't change valid
|
else ReservationValidM = ReservationValidW; // otherwise don't change valid
|
||||||
end
|
end
|
||||||
flopenrc #(`PA_BITS-2) resadrreg(clk, reset, FlushW, lrM, MemPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid
|
flopenrc #(`PA_BITS-2) resadrreg(clk, reset, FlushW, lrM, MemPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid
|
||||||
flopenrc #(1) resvldreg(clk, reset, FlushW, lrM, ReservationValidM, ReservationValidW);
|
flopenrc #(1) resvldreg(clk, reset, FlushW, lrM, ReservationValidM, ReservationValidW);
|
||||||
flopenrc #(1) squashreg(clk, reset, FlushW, ~CPUBusy, SquashSCM, SquashSCW);
|
flopenrc #(1) squashreg(clk, reset, FlushW, ~CPUBusy, SquashSCM, SquashSCW);
|
||||||
end else begin // Atomic operations not supported
|
|
||||||
assign SquashSCW = 0;
|
|
||||||
assign MemRWMtoDCache = MemRWMtoLRSC;
|
|
||||||
end
|
|
||||||
endgenerate
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|||||||
@ -42,7 +42,6 @@ module lsu
|
|||||||
input logic ExceptionM,
|
input logic ExceptionM,
|
||||||
input logic PendingInterruptM,
|
input logic PendingInterruptM,
|
||||||
input logic FlushDCacheM,
|
input logic FlushDCacheM,
|
||||||
output logic CommittedM,
|
|
||||||
output logic SquashSCW,
|
output logic SquashSCW,
|
||||||
output logic DCacheMiss,
|
output logic DCacheMiss,
|
||||||
output logic DCacheAccess,
|
output logic DCacheAccess,
|
||||||
@ -63,13 +62,13 @@ module lsu
|
|||||||
output logic StoreMisalignedFaultM, StoreAccessFaultM,
|
output logic StoreMisalignedFaultM, StoreAccessFaultM,
|
||||||
|
|
||||||
// connect to ahb
|
// connect to ahb
|
||||||
output logic [`PA_BITS-1:0] DCtoAHBPAdrM,
|
(* mark_debug = "true" *) output logic [`PA_BITS-1:0] LsuBusAdr,
|
||||||
output logic DCtoAHBReadM,
|
output logic LsuBusRead,
|
||||||
output logic DCtoAHBWriteM,
|
output logic LsuBusWrite,
|
||||||
input logic DCfromAHBAck,
|
input logic LsuBusAck,
|
||||||
input logic [`XLEN-1:0] DCfromAHBReadData,
|
(* mark_debug = "true" *) input logic [`XLEN-1:0] LsuBusHRDATA,
|
||||||
output logic [`XLEN-1:0] DCtoAHBWriteData,
|
output logic [`XLEN-1:0] LsuBusHWDATA,
|
||||||
output logic [2:0] DCtoAHBSizeM,
|
output logic [2:0] LsuBusSize,
|
||||||
|
|
||||||
// mmu management
|
// mmu management
|
||||||
|
|
||||||
@ -83,9 +82,6 @@ module lsu
|
|||||||
output logic [`XLEN-1:0] PTE,
|
output logic [`XLEN-1:0] PTE,
|
||||||
output logic [1:0] PageType,
|
output logic [1:0] PageType,
|
||||||
output logic ITLBWriteF,
|
output logic ITLBWriteF,
|
||||||
output logic WalkerInstrPageFaultF,
|
|
||||||
output logic WalkerLoadPageFaultM,
|
|
||||||
output logic WalkerStorePageFaultM,
|
|
||||||
|
|
||||||
input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
|
input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
|
||||||
input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // *** this one especially has a large note attached to it in pmpchecker.
|
input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // *** this one especially has a large note attached to it in pmpchecker.
|
||||||
@ -97,189 +93,215 @@ module lsu
|
|||||||
logic [`XLEN+1:0] IEUAdrExtM;
|
logic [`XLEN+1:0] IEUAdrExtM;
|
||||||
logic DTLBMissM;
|
logic DTLBMissM;
|
||||||
logic DTLBWriteM;
|
logic DTLBWriteM;
|
||||||
logic HPTWStall;
|
|
||||||
logic [`PA_BITS-1:0] HPTWAdr;
|
logic [1:0] DCRWM;
|
||||||
logic HPTWRead;
|
logic [1:0] LsuRWM;
|
||||||
logic [1:0] MemRWMtoDCache;
|
logic [2:0] LsuFunct3M;
|
||||||
logic [1:0] MemRWMtoLRSC;
|
logic [1:0] LsuAtomicM;
|
||||||
logic [2:0] Funct3MtoDCache;
|
logic [`PA_BITS-1:0] LsuPAdrM;
|
||||||
logic [1:0] AtomicMtoDCache;
|
logic [11:0] LsuAdrE, DCAdrE;
|
||||||
logic [`PA_BITS-1:0] MemPAdrNoTranslate;
|
|
||||||
logic [11:0] MemAdrE, MemAdrE_RENAME;
|
|
||||||
logic CPUBusy;
|
logic CPUBusy;
|
||||||
logic MemReadM;
|
logic MemReadM;
|
||||||
logic DataMisalignedM;
|
logic DataMisalignedM;
|
||||||
logic DCacheStall;
|
logic DCacheStall;
|
||||||
|
|
||||||
logic CacheableM;
|
logic CacheableM;
|
||||||
logic CacheableMtoDCache;
|
|
||||||
logic SelHPTW;
|
logic SelHPTW;
|
||||||
logic [2:0] HPTWSize;
|
|
||||||
|
|
||||||
|
|
||||||
logic CommittedMfromDCache;
|
logic BusStall;
|
||||||
logic PendingInterruptMtoDCache;
|
|
||||||
logic WalkerPageFaultM;
|
|
||||||
|
|
||||||
logic AnyCPUReqM;
|
|
||||||
logic MemAfterIWalkDone;
|
|
||||||
|
|
||||||
typedef enum {STATE_T0_READY,
|
|
||||||
STATE_T0_REPLAY,
|
|
||||||
STATE_T0_FAULT_REPLAY,
|
|
||||||
STATE_T3_DTLB_MISS,
|
|
||||||
STATE_T4_ITLB_MISS,
|
|
||||||
STATE_T5_ITLB_MISS,
|
|
||||||
STATE_T7_DITLB_MISS} statetype;
|
|
||||||
|
|
||||||
statetype CurrState, NextState;
|
|
||||||
logic InterlockStall;
|
logic InterlockStall;
|
||||||
logic SelReplayCPURequest;
|
|
||||||
logic WalkerInstrPageFaultRaw;
|
|
||||||
logic IgnoreRequest;
|
logic IgnoreRequest;
|
||||||
|
|
||||||
assign AnyCPUReqM = (|MemRWM) | (|AtomicM);
|
|
||||||
|
|
||||||
always_ff @(posedge clk)
|
|
||||||
if (reset) CurrState <= #1 STATE_T0_READY;
|
|
||||||
else CurrState <= #1 NextState;
|
|
||||||
|
|
||||||
always_comb begin
|
|
||||||
case(CurrState)
|
|
||||||
STATE_T0_READY: if(~ITLBMissF & DTLBMissM & AnyCPUReqM) NextState = STATE_T3_DTLB_MISS;
|
|
||||||
else if(ITLBMissF & ~DTLBMissM & ~AnyCPUReqM) NextState = STATE_T4_ITLB_MISS;
|
|
||||||
else if(ITLBMissF & ~DTLBMissM & AnyCPUReqM) NextState = STATE_T5_ITLB_MISS;
|
|
||||||
else if(ITLBMissF & DTLBMissM & AnyCPUReqM) NextState = STATE_T7_DITLB_MISS;
|
|
||||||
else NextState = STATE_T0_READY;
|
|
||||||
STATE_T0_REPLAY: if(DCacheStall) NextState = STATE_T0_REPLAY;
|
|
||||||
else NextState = STATE_T0_READY;
|
|
||||||
STATE_T3_DTLB_MISS: if(WalkerLoadPageFaultM | WalkerStorePageFaultM) NextState = STATE_T0_READY;
|
|
||||||
else if(DTLBWriteM) NextState = STATE_T0_REPLAY;
|
|
||||||
else NextState = STATE_T3_DTLB_MISS;
|
|
||||||
STATE_T4_ITLB_MISS: if(WalkerInstrPageFaultRaw | ITLBWriteF) NextState = STATE_T0_READY;
|
|
||||||
else NextState = STATE_T4_ITLB_MISS;
|
|
||||||
STATE_T5_ITLB_MISS: if(ITLBWriteF) NextState = STATE_T0_REPLAY;
|
|
||||||
else if(WalkerInstrPageFaultRaw) NextState = STATE_T0_FAULT_REPLAY;
|
|
||||||
else NextState = STATE_T5_ITLB_MISS;
|
|
||||||
STATE_T0_FAULT_REPLAY: if(DCacheStall) NextState = STATE_T0_FAULT_REPLAY;
|
|
||||||
else NextState = STATE_T0_READY;
|
|
||||||
STATE_T7_DITLB_MISS: if(WalkerStorePageFaultM | WalkerLoadPageFaultM) NextState = STATE_T0_READY;
|
|
||||||
else if(DTLBWriteM) NextState = STATE_T5_ITLB_MISS;
|
|
||||||
else NextState = STATE_T7_DITLB_MISS;
|
|
||||||
default: NextState = STATE_T0_READY;
|
|
||||||
endcase
|
|
||||||
end // always_comb
|
|
||||||
|
|
||||||
// signal to CPU it needs to wait on HPTW.
|
|
||||||
/* -----\/----- EXCLUDED -----\/-----
|
|
||||||
// this code has a problem with imperas64mmu as it reads in an invalid uninitalized instruction. InterlockStall becomes x and it propagates
|
|
||||||
// everywhere. The case statement below implements the same logic but any x on the inputs will resolve to 0.
|
|
||||||
assign InterlockStall = (CurrState == STATE_T0_READY & (DTLBMissM | ITLBMissF)) |
|
|
||||||
(CurrState == STATE_T3_DTLB_MISS & ~WalkerPageFaultM) | (CurrState == STATE_T4_ITLB_MISS & ~WalkerInstrPageFaultRaw) |
|
|
||||||
(CurrState == STATE_T5_ITLB_MISS & ~WalkerInstrPageFaultRaw) | (CurrState == STATE_T7_DITLB_MISS & ~WalkerPageFaultM);
|
|
||||||
|
|
||||||
-----/\----- EXCLUDED -----/\----- */
|
|
||||||
|
|
||||||
always_comb begin
|
|
||||||
InterlockStall = 1'b0;
|
|
||||||
case(CurrState)
|
|
||||||
STATE_T0_READY: if(DTLBMissM | ITLBMissF) InterlockStall = 1'b1;
|
|
||||||
STATE_T3_DTLB_MISS: if (~WalkerPageFaultM) InterlockStall = 1'b1;
|
|
||||||
STATE_T4_ITLB_MISS: if (~WalkerInstrPageFaultRaw) InterlockStall = 1'b1;
|
|
||||||
STATE_T5_ITLB_MISS: InterlockStall = 1'b1;
|
|
||||||
//STATE_T0_FAULT_REPLAY: if (~WalkerInstrPageFaultF) InterlockStall = 1'b1;
|
|
||||||
STATE_T7_DITLB_MISS: if (~WalkerPageFaultM) InterlockStall = 1'b1;
|
|
||||||
default: InterlockStall = 1'b0;
|
|
||||||
endcase
|
|
||||||
end
|
|
||||||
|
|
||||||
|
|
||||||
// When replaying CPU memory request after PTW select the IEUAdrM for correct address.
|
|
||||||
assign SelReplayCPURequest = (NextState == STATE_T0_REPLAY) | (NextState == STATE_T0_FAULT_REPLAY);
|
|
||||||
assign SelHPTW = (CurrState == STATE_T3_DTLB_MISS) | (CurrState == STATE_T4_ITLB_MISS) |
|
|
||||||
(CurrState == STATE_T5_ITLB_MISS) | (CurrState == STATE_T7_DITLB_MISS);
|
|
||||||
assign IgnoreRequest = (CurrState == STATE_T0_READY & (ITLBMissF | DTLBMissM | ExceptionM | PendingInterruptM)) |
|
|
||||||
((CurrState == STATE_T0_REPLAY | CurrState == STATE_T0_FAULT_REPLAY)
|
|
||||||
& (ExceptionM | PendingInterruptM));
|
|
||||||
|
|
||||||
assign WalkerInstrPageFaultF = WalkerInstrPageFaultRaw | CurrState == STATE_T0_FAULT_REPLAY;
|
|
||||||
|
|
||||||
|
|
||||||
flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
|
flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
|
||||||
|
|
||||||
// *** add generate to conditionally create hptw, lsuArb, and mmu
|
|
||||||
// based on `MEM_VIRTMEM
|
|
||||||
hptw hptw(.clk, .reset, .SATP_REGW, .PCF, .IEUAdrM,
|
|
||||||
.ITLBMissF(ITLBMissF & ~PendingInterruptM),
|
|
||||||
.DTLBMissM(DTLBMissM & ~PendingInterruptM),
|
|
||||||
.MemRWM, .PTE, .PageType, .ITLBWriteF, .DTLBWriteM,
|
|
||||||
.HPTWReadPTE(ReadDataM),
|
|
||||||
.DCacheStall, .HPTWAdr, .HPTWRead, .HPTWSize, .AnyCPUReqM,
|
|
||||||
.WalkerInstrPageFaultF(WalkerInstrPageFaultRaw),
|
|
||||||
.WalkerLoadPageFaultM, .WalkerStorePageFaultM);
|
|
||||||
|
|
||||||
assign LSUStall = DCacheStall | InterlockStall;
|
|
||||||
|
|
||||||
assign WalkerPageFaultM = WalkerStorePageFaultM | WalkerLoadPageFaultM;
|
|
||||||
|
|
||||||
// arbiter between IEU and hptw
|
|
||||||
|
|
||||||
// multiplex the outputs to LSU
|
|
||||||
assign MemRWMtoLRSC = SelHPTW ? {HPTWRead, 1'b0} : MemRWM;
|
|
||||||
|
|
||||||
mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, Funct3MtoDCache);
|
|
||||||
|
|
||||||
// this is for the d cache SRAM.
|
|
||||||
// turns out because we cannot pipeline hptw requests we don't need this register
|
|
||||||
//flop #(`PA_BITS) HPTWAdrMReg(clk, HPTWAdr, HPTWAdrM); // delay HPTWAdrM by a cycle
|
|
||||||
|
|
||||||
assign AtomicMtoDCache = SelHPTW ? 2'b00 : AtomicM;
|
|
||||||
assign IEUAdrExtM = {2'b00, IEUAdrM};
|
assign IEUAdrExtM = {2'b00, IEUAdrM};
|
||||||
assign MemPAdrNoTranslate = SelHPTW ? HPTWAdr : IEUAdrExtM[`PA_BITS-1:0];
|
|
||||||
assign MemAdrE = SelHPTW ? HPTWAdr[11:0] : IEUAdrE[11:0];
|
|
||||||
assign CPUBusy = SelHPTW ? 1'b0 : StallW;
|
|
||||||
// always block interrupts when using the hardware page table walker.
|
|
||||||
assign CommittedM = SelHPTW ? 1'b1 : CommittedMfromDCache;
|
|
||||||
|
|
||||||
|
generate
|
||||||
|
if(`MEM_VIRTMEM) begin : MEM_VIRTMEM
|
||||||
|
logic AnyCPUReqM;
|
||||||
|
logic [`PA_BITS-1:0] HPTWAdr;
|
||||||
|
logic HPTWRead;
|
||||||
|
logic [2:0] HPTWSize;
|
||||||
|
logic SelReplayCPURequest;
|
||||||
|
|
||||||
assign PendingInterruptMtoDCache = SelHPTW ? 1'b0 : PendingInterruptM;
|
typedef enum {STATE_T0_READY,
|
||||||
|
STATE_T0_REPLAY,
|
||||||
|
STATE_T3_DTLB_MISS,
|
||||||
|
STATE_T4_ITLB_MISS,
|
||||||
|
STATE_T5_ITLB_MISS,
|
||||||
|
STATE_T7_DITLB_MISS} statetype;
|
||||||
|
|
||||||
|
statetype InterlockCurrState, InterlockNextState;
|
||||||
|
|
||||||
|
assign AnyCPUReqM = (|MemRWM) | (|AtomicM);
|
||||||
|
|
||||||
|
always_ff @(posedge clk)
|
||||||
|
if (reset) InterlockCurrState <= #1 STATE_T0_READY;
|
||||||
|
else InterlockCurrState <= #1 InterlockNextState;
|
||||||
|
|
||||||
|
always_comb begin
|
||||||
|
case(InterlockCurrState)
|
||||||
|
STATE_T0_READY: if(~ITLBMissF & DTLBMissM & AnyCPUReqM) InterlockNextState = STATE_T3_DTLB_MISS;
|
||||||
|
else if(ITLBMissF & ~DTLBMissM & ~AnyCPUReqM) InterlockNextState = STATE_T4_ITLB_MISS;
|
||||||
|
else if(ITLBMissF & ~DTLBMissM & AnyCPUReqM) InterlockNextState = STATE_T5_ITLB_MISS;
|
||||||
|
else if(ITLBMissF & DTLBMissM & AnyCPUReqM) InterlockNextState = STATE_T7_DITLB_MISS;
|
||||||
|
else InterlockNextState = STATE_T0_READY;
|
||||||
|
STATE_T0_REPLAY: if(DCacheStall) InterlockNextState = STATE_T0_REPLAY;
|
||||||
|
else InterlockNextState = STATE_T0_READY;
|
||||||
|
STATE_T3_DTLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T0_REPLAY;
|
||||||
|
else InterlockNextState = STATE_T3_DTLB_MISS;
|
||||||
|
STATE_T4_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T0_READY;
|
||||||
|
else InterlockNextState = STATE_T4_ITLB_MISS;
|
||||||
|
STATE_T5_ITLB_MISS: if(ITLBWriteF) InterlockNextState = STATE_T0_REPLAY;
|
||||||
|
else InterlockNextState = STATE_T5_ITLB_MISS;
|
||||||
|
STATE_T7_DITLB_MISS: if(DTLBWriteM) InterlockNextState = STATE_T5_ITLB_MISS;
|
||||||
|
else InterlockNextState = STATE_T7_DITLB_MISS;
|
||||||
|
default: InterlockNextState = STATE_T0_READY;
|
||||||
|
endcase
|
||||||
|
end // always_comb
|
||||||
|
|
||||||
|
// signal to CPU it needs to wait on HPTW.
|
||||||
|
/* -----\/----- EXCLUDED -----\/-----
|
||||||
|
// this code has a problem with imperas64mmu as it reads in an invalid uninitalized instruction. InterlockStall becomes x and it propagates
|
||||||
|
// everywhere. The case statement below implements the same logic but any x on the inputs will resolve to 0.
|
||||||
|
assign InterlockStall = (InterlockCurrState == STATE_T0_READY & (DTLBMissM | ITLBMissF)) |
|
||||||
|
(InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) |
|
||||||
|
(InterlockCurrState == STATE_T5_ITLB_MISS) | (InterlockCurrState == STATE_T7_DITLB_MISS);
|
||||||
|
|
||||||
|
-----/\----- EXCLUDED -----/\----- */
|
||||||
|
|
||||||
|
always_comb begin
|
||||||
|
InterlockStall = 1'b0;
|
||||||
|
case(InterlockCurrState)
|
||||||
|
STATE_T0_READY: if(DTLBMissM | ITLBMissF) InterlockStall = 1'b1;
|
||||||
|
STATE_T3_DTLB_MISS: InterlockStall = 1'b1;
|
||||||
|
STATE_T4_ITLB_MISS: InterlockStall = 1'b1;
|
||||||
|
STATE_T5_ITLB_MISS: InterlockStall = 1'b1;
|
||||||
|
STATE_T7_DITLB_MISS: InterlockStall = 1'b1;
|
||||||
|
default: InterlockStall = 1'b0;
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
|
|
||||||
|
// When replaying CPU memory request after PTW select the IEUAdrM for correct address.
|
||||||
|
assign SelReplayCPURequest = (InterlockNextState == STATE_T0_REPLAY);
|
||||||
|
assign SelHPTW = (InterlockCurrState == STATE_T3_DTLB_MISS) | (InterlockCurrState == STATE_T4_ITLB_MISS) |
|
||||||
|
(InterlockCurrState == STATE_T5_ITLB_MISS) | (InterlockCurrState == STATE_T7_DITLB_MISS);
|
||||||
|
assign IgnoreRequest = (InterlockCurrState == STATE_T0_READY & (ITLBMissF | DTLBMissM | ExceptionM | PendingInterruptM)) |
|
||||||
|
((InterlockCurrState == STATE_T0_REPLAY)
|
||||||
|
& (ExceptionM | PendingInterruptM));
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
// *** add generate to conditionally create hptw, lsuArb, and mmu
|
||||||
|
// based on `MEM_VIRTMEM
|
||||||
|
hptw hptw(.clk, .reset, .SATP_REGW, .PCF, .IEUAdrM,
|
||||||
|
.ITLBMissF(ITLBMissF & ~PendingInterruptM),
|
||||||
|
.DTLBMissM(DTLBMissM & ~PendingInterruptM),
|
||||||
|
.MemRWM, .PTE, .PageType, .ITLBWriteF, .DTLBWriteM,
|
||||||
|
.HPTWReadPTE(ReadDataM),
|
||||||
|
.DCacheStall, .HPTWAdr, .HPTWRead, .HPTWSize, .AnyCPUReqM);
|
||||||
|
|
||||||
|
// arbiter between IEU and hptw
|
||||||
|
|
||||||
|
// multiplex the outputs to LSU
|
||||||
|
mux2 #(2) rwmux(MemRWM, {HPTWRead, 1'b0}, SelHPTW, LsuRWM);
|
||||||
|
mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LsuFunct3M);
|
||||||
|
mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LsuAtomicM);
|
||||||
|
mux2 #(12) adremux(IEUAdrE[11:0], HPTWAdr[11:0], SelHPTW, LsuAdrE);
|
||||||
|
mux2 #(`PA_BITS) lsupadrmux(IEUAdrExtM[`PA_BITS-1:0], HPTWAdr, SelHPTW, LsuPAdrM);
|
||||||
|
|
||||||
|
assign CPUBusy = StallW & ~SelHPTW;
|
||||||
|
// always block interrupts when using the hardware page table walker.
|
||||||
|
|
||||||
|
// this is for the d cache SRAM.
|
||||||
|
// turns out because we cannot pipeline hptw requests we don't need this register
|
||||||
|
//flop #(`PA_BITS) HPTWAdrMReg(clk, HPTWAdr, HPTWAdrM); // delay HPTWAdrM by a cycle
|
||||||
|
|
||||||
|
//assign LsuRWM = SelHPTW ? {HPTWRead, 1'b0} : MemRWM;
|
||||||
|
//assign LsuAdrE = SelHPTW ? HPTWAdr[11:0] : IEUAdrE[11:0];
|
||||||
|
//assign LsuAtomicM = SelHPTW ? 2'b00 : AtomicM;
|
||||||
|
//assign LsuPAdrM = SelHPTW ? HPTWAdr : IEUAdrExtM[`PA_BITS-1:0];
|
||||||
|
|
||||||
|
|
||||||
|
// Specify which type of page fault is occurring
|
||||||
|
// *** `MEM_VIRTMEM
|
||||||
|
assign DTLBLoadPageFaultM = DTLBPageFaultM & LsuRWM[1];
|
||||||
|
assign DTLBStorePageFaultM = DTLBPageFaultM & LsuRWM[0];
|
||||||
|
|
||||||
|
assign DCAdrE = SelReplayCPURequest ? IEUAdrM[11:0] : LsuAdrE;
|
||||||
|
|
||||||
|
end // if (`MEM_VIRTMEM)
|
||||||
|
else begin
|
||||||
|
assign InterlockStall = 1'b0;
|
||||||
|
|
||||||
|
assign DCAdrE = LsuAdrE;
|
||||||
|
assign SelHPTW = 1'b0;
|
||||||
|
assign IgnoreRequest = 1'b0;
|
||||||
|
|
||||||
|
assign PTE = '0;
|
||||||
|
assign PageType = '0;
|
||||||
|
assign DTLBWriteM = 1'b0;
|
||||||
|
assign ITLBWriteF = 1'b0;
|
||||||
|
|
||||||
|
assign LsuRWM = MemRWM;
|
||||||
|
assign LsuFunct3M = Funct3M;
|
||||||
|
assign LsuAtomicM = AtomicM;
|
||||||
|
assign LsuAdrE = IEUAdrE[11:0];
|
||||||
|
assign LsuPAdrM = IEUAdrExtM;
|
||||||
|
assign CPUBusy = StallW;
|
||||||
|
|
||||||
|
assign DTLBLoadPageFaultM = 1'b0;
|
||||||
|
assign DTLBStorePageFaultM = 1'b0;
|
||||||
|
end
|
||||||
|
endgenerate
|
||||||
|
|
||||||
|
|
||||||
mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
|
mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
|
||||||
dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
|
dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
|
||||||
.PrivilegeModeW, .DisableTranslation(SelHPTW),
|
.PrivilegeModeW, .DisableTranslation(SelHPTW),
|
||||||
.PAdr(MemPAdrNoTranslate),
|
.PAdr(LsuPAdrM),
|
||||||
.VAdr(IEUAdrM),
|
.VAdr(IEUAdrM),
|
||||||
.Size(Funct3MtoDCache[1:0]),
|
.Size(LsuFunct3M[1:0]),
|
||||||
.PTE,
|
.PTE,
|
||||||
.PageTypeWriteVal(PageType),
|
.PageTypeWriteVal(PageType),
|
||||||
.TLBWrite(DTLBWriteM),
|
.TLBWrite(DTLBWriteM),
|
||||||
.TLBFlush(DTLBFlushM),
|
.TLBFlush(DTLBFlushM),
|
||||||
.PhysicalAddress(MemPAdrM),
|
.PhysicalAddress(MemPAdrM),
|
||||||
.TLBMiss(DTLBMissM),
|
.TLBMiss(DTLBMissM),
|
||||||
.Cacheable(CacheableM),
|
.Cacheable(CacheableM),
|
||||||
.Idempotent(), .AtomicAllowed(),
|
.Idempotent(), .AtomicAllowed(),
|
||||||
.TLBPageFault(DTLBPageFaultM),
|
.TLBPageFault(DTLBPageFaultM),
|
||||||
.InstrAccessFaultF(), .LoadAccessFaultM, .StoreAccessFaultM,
|
.InstrAccessFaultF(), .LoadAccessFaultM, .StoreAccessFaultM,
|
||||||
.AtomicAccessM(1'b0), .ExecuteAccessF(1'b0),
|
.AtomicAccessM(1'b0), .ExecuteAccessF(1'b0),
|
||||||
.WriteAccessM(MemRWMtoLRSC[0]), .ReadAccessM(MemRWMtoLRSC[1]),
|
.WriteAccessM(LsuRWM[0]), .ReadAccessM(LsuRWM[1]),
|
||||||
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW
|
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW
|
||||||
); // *** the pma/pmp instruction access faults don't really matter here. is it possible to parameterize which outputs exist?
|
); // *** the pma/pmp instruction access faults don't really matter here. is it possible to parameterize which outputs exist?
|
||||||
|
|
||||||
|
assign LSUStall = DCacheStall | InterlockStall | BusStall;
|
||||||
|
|
||||||
|
|
||||||
|
// If the CPU's (not HPTW's) request is a page fault.
|
||||||
|
assign LoadMisalignedFaultM = DataMisalignedM & MemRWM[1];
|
||||||
|
assign StoreMisalignedFaultM = DataMisalignedM & MemRWM[0];
|
||||||
|
|
||||||
|
|
||||||
// Move generate from lrsc to outside this module.
|
// Move generate from lrsc to outside this module.
|
||||||
assign MemReadM = MemRWMtoLRSC[1] & ~(ExceptionM | PendingInterruptMtoDCache) & ~DTLBMissM; // & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED;
|
generate
|
||||||
lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .MemRWMtoLRSC, .AtomicMtoDCache, .MemPAdrM,
|
if (`A_SUPPORTED) begin
|
||||||
.SquashSCW, .MemRWMtoDCache);
|
assign MemReadM = LsuRWM[1] & ~(IgnoreRequest) & ~DTLBMissM;
|
||||||
|
lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .LsuRWM, .LsuAtomicM, .MemPAdrM,
|
||||||
|
.SquashSCW, .DCRWM);
|
||||||
|
end else begin
|
||||||
|
assign SquashSCW = 0;
|
||||||
|
assign DCRWM = LsuRWM;
|
||||||
|
end
|
||||||
|
endgenerate
|
||||||
|
|
||||||
// *** BUG, this is most likely wrong
|
|
||||||
assign CacheableMtoDCache = SelHPTW ? 1'b1 : CacheableM;
|
|
||||||
|
|
||||||
|
|
||||||
// Specify which type of page fault is occurring
|
|
||||||
// *** `MEM_VIRTMEM
|
|
||||||
assign DTLBLoadPageFaultM = DTLBPageFaultM & MemRWMtoLRSC[1];
|
|
||||||
assign DTLBStorePageFaultM = DTLBPageFaultM & MemRWMtoLRSC[0];
|
|
||||||
|
|
||||||
// Determine if an Unaligned access is taking place
|
// Determine if an Unaligned access is taking place
|
||||||
// hptw guarantees alignment, only check inputs from IEU.
|
// hptw guarantees alignment, only check inputs from IEU.
|
||||||
@ -291,39 +313,252 @@ module lsu
|
|||||||
2'b11: DataMisalignedM = |IEUAdrM[2:0]; // ld, sd, fld, fsd
|
2'b11: DataMisalignedM = |IEUAdrM[2:0]; // ld, sd, fld, fsd
|
||||||
endcase
|
endcase
|
||||||
|
|
||||||
// Determine if address is valid
|
|
||||||
assign LoadMisalignedFaultM = DataMisalignedM & MemRWMtoLRSC[1];
|
|
||||||
assign StoreMisalignedFaultM = DataMisalignedM & MemRWMtoLRSC[0];
|
|
||||||
|
|
||||||
// conditional
|
// conditional
|
||||||
// 1. ram // controlled by `MEM_DTIM
|
// 1. ram // controlled by `MEM_DTIM
|
||||||
// 2. cache `MEM_DCACHE
|
// 2. cache `MEM_DCACHE
|
||||||
// 3. wire pass-through
|
// 3. wire pass-through
|
||||||
assign MemAdrE_RENAME = SelReplayCPURequest ? IEUAdrM[11:0] : MemAdrE[11:0];
|
|
||||||
|
localparam integer WORDSPERLINE = `DCACHE_BLOCKLENINBITS/`XLEN;
|
||||||
|
localparam integer LOGWPL = $clog2(WORDSPERLINE);
|
||||||
|
localparam integer BLOCKLEN = `DCACHE_BLOCKLENINBITS;
|
||||||
|
|
||||||
|
localparam integer FetchCountThreshold = WORDSPERLINE - 1;
|
||||||
|
localparam integer BLOCKBYTELEN = BLOCKLEN/8;
|
||||||
|
localparam integer OFFSETLEN = $clog2(BLOCKBYTELEN);
|
||||||
|
|
||||||
|
// temp
|
||||||
|
logic SelUncached;
|
||||||
|
logic FetchCountFlag;
|
||||||
|
|
||||||
|
logic [`XLEN-1:0] FinalAMOWriteDataM, FinalWriteDataM;
|
||||||
|
(* mark_debug = "true" *) logic [`XLEN-1:0] DC_HWDATA_FIXNAME;
|
||||||
|
logic SelFlush;
|
||||||
|
logic [`XLEN-1:0] ReadDataWordM;
|
||||||
|
logic [`DCACHE_BLOCKLENINBITS-1:0] DCacheMemWriteData;
|
||||||
|
|
||||||
|
// keep
|
||||||
|
logic [`XLEN-1:0] ReadDataWordMuxM;
|
||||||
|
|
||||||
|
|
||||||
|
logic [LOGWPL-1:0] FetchCount, NextFetchCount;
|
||||||
|
logic [`PA_BITS-1:0] BasePAdrMaskedM;
|
||||||
|
logic [OFFSETLEN-1:0] BasePAdrOffsetM;
|
||||||
|
|
||||||
|
logic CntEn, PreCntEn;
|
||||||
|
logic CntReset;
|
||||||
|
logic [`PA_BITS-1:0] BasePAdrM;
|
||||||
|
logic [`XLEN-1:0] ReadDataBlockSetsM [(`DCACHE_BLOCKLENINBITS/`XLEN)-1:0];
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
logic DCWriteLine;
|
||||||
|
logic DCFetchLine;
|
||||||
|
logic BUSACK;
|
||||||
|
|
||||||
dcache dcache(.clk, .reset, .CPUBusy,
|
dcache dcache(.clk, .reset, .CPUBusy,
|
||||||
.MemRWM(MemRWMtoDCache),
|
.MemRWM(DCRWM),
|
||||||
.Funct3M(Funct3MtoDCache),
|
.Funct3M(LsuFunct3M),
|
||||||
.Funct7M, .FlushDCacheM,
|
.Funct7M, .FlushDCacheM,
|
||||||
.AtomicM(AtomicMtoDCache),
|
.AtomicM(LsuAtomicM),
|
||||||
.MemAdrE(MemAdrE_RENAME),
|
.MemAdrE(DCAdrE),
|
||||||
.MemPAdrM,
|
.MemPAdrM,
|
||||||
.VAdr(IEUAdrM[11:0]), // this will be removed once the dcache hptw interlock is removed.
|
.FinalWriteDataM, .ReadDataWordM, .DCacheStall,
|
||||||
.WriteDataM, .ReadDataM, .DCacheStall,
|
.DCacheMiss, .DCacheAccess, .IgnoreRequest,
|
||||||
.CommittedM(CommittedMfromDCache),
|
.CacheableM(CacheableM),
|
||||||
.DCacheMiss, .DCacheAccess, .ExceptionM, .IgnoreRequest,
|
|
||||||
.PendingInterruptM(PendingInterruptMtoDCache),
|
|
||||||
.CacheableM(CacheableMtoDCache),
|
|
||||||
|
|
||||||
// AHB connection
|
.BasePAdrM,
|
||||||
.AHBPAdr(DCtoAHBPAdrM),
|
.ReadDataBlockSetsM,
|
||||||
.AHBRead(DCtoAHBReadM),
|
.SelFlush,
|
||||||
.AHBWrite(DCtoAHBWriteM),
|
.DCacheMemWriteData,
|
||||||
.AHBAck(DCfromAHBAck),
|
.DCFetchLine,
|
||||||
.HWDATA(DCtoAHBWriteData),
|
.DCWriteLine,
|
||||||
.HRDATA(DCfromAHBReadData),
|
.BUSACK
|
||||||
.DCtoAHBSizeM
|
|
||||||
);
|
);
|
||||||
|
|
||||||
|
|
||||||
|
mux2 #(`XLEN) UnCachedDataMux(.d0(ReadDataWordM),
|
||||||
|
.d1(DCacheMemWriteData[`XLEN-1:0]),
|
||||||
|
.s(SelUncached),
|
||||||
|
.y(ReadDataWordMuxM));
|
||||||
|
|
||||||
|
// finally swr
|
||||||
|
subwordread subwordread(.ReadDataWordMuxM,
|
||||||
|
.MemPAdrM(MemPAdrM[2:0]),
|
||||||
|
.Funct3M(LsuFunct3M),
|
||||||
|
.ReadDataM);
|
||||||
|
|
||||||
|
generate
|
||||||
|
if (`A_SUPPORTED) begin
|
||||||
|
logic [`XLEN-1:0] AMOResult;
|
||||||
|
amoalu amoalu(.srca(ReadDataM), .srcb(WriteDataM), .funct(Funct7M), .width(LsuFunct3M[1:0]),
|
||||||
|
.result(AMOResult));
|
||||||
|
mux2 #(`XLEN) wdmux(WriteDataM, AMOResult, LsuAtomicM[1], FinalAMOWriteDataM);
|
||||||
|
end else
|
||||||
|
assign FinalAMOWriteDataM = WriteDataM;
|
||||||
|
endgenerate
|
||||||
|
|
||||||
|
subwordwrite subwordwrite(.HRDATA(ReadDataWordM),
|
||||||
|
.HADDRD(MemPAdrM[2:0]),
|
||||||
|
.HSIZED({LsuFunct3M[2], 1'b0, LsuFunct3M[1:0]}),
|
||||||
|
.HWDATAIN(FinalAMOWriteDataM),
|
||||||
|
.HWDATA(FinalWriteDataM));
|
||||||
|
|
||||||
|
assign LsuBusHWDATA = CacheableM | SelFlush ? DC_HWDATA_FIXNAME : WriteDataM;
|
||||||
|
|
||||||
|
generate
|
||||||
|
if (`XLEN == 32) assign LsuBusSize = CacheableM | SelFlush ? 3'b010 : LsuFunct3M;
|
||||||
|
else assign LsuBusSize = CacheableM | SelFlush ? 3'b011 : LsuFunct3M;
|
||||||
|
endgenerate;
|
||||||
|
|
||||||
|
// Bus Side logic
|
||||||
|
// register the fetch data from the next level of memory.
|
||||||
|
// This register should be necessary for timing. There is no register in the uncore or
|
||||||
|
// ahblite controller between the memories and this cache.
|
||||||
|
|
||||||
|
genvar index;
|
||||||
|
generate
|
||||||
|
for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
|
||||||
|
flopen #(`XLEN) fb(.clk(clk),
|
||||||
|
.en(LsuBusAck & LsuBusRead & (index == FetchCount)),
|
||||||
|
.d(LsuBusHRDATA),
|
||||||
|
.q(DCacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN]));
|
||||||
|
end
|
||||||
|
endgenerate
|
||||||
|
|
||||||
|
|
||||||
|
// if not cacheable the offset bits needs to be sent to the EBU.
|
||||||
|
// if cacheable the offset bits are discarded. $ FSM will fetch the whole block.
|
||||||
|
assign BasePAdrOffsetM = CacheableM ? {{OFFSETLEN}{1'b0}} : BasePAdrM[OFFSETLEN-1:0];
|
||||||
|
assign BasePAdrMaskedM = {BasePAdrM[`PA_BITS-1:OFFSETLEN], BasePAdrOffsetM};
|
||||||
|
|
||||||
|
assign LsuBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, FetchCount} << $clog2(`XLEN/8)) + BasePAdrMaskedM;
|
||||||
|
|
||||||
|
assign DC_HWDATA_FIXNAME = ReadDataBlockSetsM[FetchCount];
|
||||||
|
|
||||||
|
assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL-1:0]);
|
||||||
|
assign CntEn = PreCntEn & LsuBusAck;
|
||||||
|
|
||||||
|
flopenr #(LOGWPL)
|
||||||
|
FetchCountReg(.clk(clk),
|
||||||
|
.reset(reset | CntReset),
|
||||||
|
.en(CntEn),
|
||||||
|
.d(NextFetchCount),
|
||||||
|
.q(FetchCount));
|
||||||
|
|
||||||
|
assign NextFetchCount = FetchCount + 1'b1;
|
||||||
|
|
||||||
|
typedef enum {STATE_BUS_READY,
|
||||||
|
STATE_BUS_FETCH,
|
||||||
|
STATE_BUS_WRITE,
|
||||||
|
STATE_BUS_UNCACHED_WRITE,
|
||||||
|
STATE_BUS_UNCACHED_WRITE_DONE,
|
||||||
|
STATE_BUS_UNCACHED_READ,
|
||||||
|
STATE_BUS_UNCACHED_READ_DONE} busstatetype;
|
||||||
|
|
||||||
|
(* mark_debug = "true" *) busstatetype BusCurrState, BusNextState;
|
||||||
|
|
||||||
|
always_ff @(posedge clk)
|
||||||
|
if (reset) BusCurrState <= #1 STATE_BUS_READY;
|
||||||
|
else BusCurrState <= #1 BusNextState;
|
||||||
|
|
||||||
|
always_comb begin
|
||||||
|
BusNextState = STATE_BUS_READY;
|
||||||
|
CntReset = 1'b0;
|
||||||
|
BusStall = 1'b0;
|
||||||
|
PreCntEn = 1'b0;
|
||||||
|
LsuBusWrite = 1'b0;
|
||||||
|
LsuBusRead = 1'b0;
|
||||||
|
BUSACK = 1'b0;
|
||||||
|
SelUncached = 1'b0;
|
||||||
|
|
||||||
|
case(BusCurrState)
|
||||||
|
STATE_BUS_READY: begin
|
||||||
|
if(IgnoreRequest) begin
|
||||||
|
BusNextState = STATE_BUS_READY;
|
||||||
|
end else
|
||||||
|
// uncache write
|
||||||
|
if(DCRWM[0] & ~CacheableM) begin
|
||||||
|
BusNextState = STATE_BUS_UNCACHED_WRITE;
|
||||||
|
CntReset = 1'b1;
|
||||||
|
BusStall = 1'b1;
|
||||||
|
LsuBusWrite = 1'b1;
|
||||||
|
end
|
||||||
|
// uncached read
|
||||||
|
else if(DCRWM[1] & ~CacheableM) begin
|
||||||
|
BusNextState = STATE_BUS_UNCACHED_READ;
|
||||||
|
CntReset = 1'b1;
|
||||||
|
BusStall = 1'b1;
|
||||||
|
LsuBusRead = 1'b1;
|
||||||
|
end
|
||||||
|
// D$ Fetch Line
|
||||||
|
else if(DCFetchLine) begin
|
||||||
|
BusNextState = STATE_BUS_FETCH;
|
||||||
|
CntReset = 1'b1;
|
||||||
|
BusStall = 1'b1;
|
||||||
|
end
|
||||||
|
// D$ Write Line
|
||||||
|
else if(DCWriteLine) begin
|
||||||
|
BusNextState = STATE_BUS_WRITE;
|
||||||
|
CntReset = 1'b1;
|
||||||
|
BusStall = 1'b1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
STATE_BUS_UNCACHED_WRITE : begin
|
||||||
|
BusStall = 1'b1;
|
||||||
|
LsuBusWrite = 1'b1;
|
||||||
|
if(LsuBusAck) begin
|
||||||
|
BusNextState = STATE_BUS_UNCACHED_WRITE_DONE;
|
||||||
|
end else begin
|
||||||
|
BusNextState = STATE_BUS_UNCACHED_WRITE;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
STATE_BUS_UNCACHED_READ: begin
|
||||||
|
BusStall = 1'b1;
|
||||||
|
LsuBusRead = 1'b1;
|
||||||
|
if(LsuBusAck) begin
|
||||||
|
BusNextState = STATE_BUS_UNCACHED_READ_DONE;
|
||||||
|
end else begin
|
||||||
|
BusNextState = STATE_BUS_UNCACHED_READ;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
STATE_BUS_UNCACHED_WRITE_DONE: begin
|
||||||
|
BusNextState = STATE_BUS_READY;
|
||||||
|
end
|
||||||
|
|
||||||
|
STATE_BUS_UNCACHED_READ_DONE: begin
|
||||||
|
SelUncached = 1'b1;
|
||||||
|
end
|
||||||
|
|
||||||
|
STATE_BUS_FETCH: begin
|
||||||
|
BusStall = 1'b1;
|
||||||
|
PreCntEn = 1'b1;
|
||||||
|
LsuBusRead = 1'b1;
|
||||||
|
|
||||||
|
if (FetchCountFlag & LsuBusAck) begin
|
||||||
|
BusNextState = STATE_BUS_READY;
|
||||||
|
BUSACK = 1'b1;
|
||||||
|
end else begin
|
||||||
|
BusNextState = STATE_BUS_FETCH;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
STATE_BUS_WRITE: begin
|
||||||
|
BusStall = 1'b1;
|
||||||
|
PreCntEn = 1'b1;
|
||||||
|
LsuBusWrite = 1'b1;
|
||||||
|
if(FetchCountFlag & LsuBusAck) begin
|
||||||
|
BusNextState = STATE_BUS_READY;
|
||||||
|
BUSACK = 1'b1;
|
||||||
|
end else begin
|
||||||
|
BusNextState = STATE_BUS_WRITE;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
|
|||||||
@ -25,99 +25,90 @@
|
|||||||
|
|
||||||
`include "wally-config.vh"
|
`include "wally-config.vh"
|
||||||
|
|
||||||
module subwordread (
|
module subwordread
|
||||||
input logic [`XLEN-1:0] ReadDataWordMuxM,
|
(
|
||||||
input logic [2:0] MemPAdrM,
|
input logic [`XLEN-1:0] ReadDataWordMuxM,
|
||||||
input logic [2:0] Funct3M,
|
input logic [2:0] MemPAdrM,
|
||||||
output logic [`XLEN-1:0] ReadDataM
|
input logic [2:0] Funct3M,
|
||||||
);
|
output logic [`XLEN-1:0] ReadDataM
|
||||||
|
);
|
||||||
logic [`XLEN-1:0] offset0, offset1, offset2, offset3;
|
|
||||||
|
logic [7:0] ByteM;
|
||||||
|
logic [15:0] HalfwordM;
|
||||||
// Funct3M[2] is the unsigned bit. mask upper bits.
|
// Funct3M[2] is the unsigned bit. mask upper bits.
|
||||||
// Funct3M[1:0] is the size of the memory access.
|
// Funct3M[1:0] is the size of the memory access.
|
||||||
|
|
||||||
generate
|
generate
|
||||||
if (`XLEN == 64) begin
|
if (`XLEN == 64) begin
|
||||||
logic [`XLEN-1:0] offset4, offset5, offset6, offset7;
|
// ByteMe mux
|
||||||
|
|
||||||
always_comb
|
always_comb
|
||||||
case(Funct3M[1:0])
|
case(MemPAdrM[2:0])
|
||||||
3: offset0 = ReadDataWordMuxM; //ld
|
3'b000: ByteM = ReadDataWordMuxM[7:0];
|
||||||
2: offset0 = Funct3M[2] ? {{32'b0}, ReadDataWordMuxM[31:0]} : {{32{ReadDataWordMuxM[31]}}, ReadDataWordMuxM[31:0]}; //lw(u)
|
3'b001: ByteM = ReadDataWordMuxM[15:8];
|
||||||
1: offset0 = Funct3M[2] ? {{48'b0}, ReadDataWordMuxM[15:0]} : {{48{ReadDataWordMuxM[15]}}, ReadDataWordMuxM[15:0]}; //lh(u)
|
3'b010: ByteM = ReadDataWordMuxM[23:16];
|
||||||
0: offset0 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[7:0]} : {{56{ReadDataWordMuxM[7]}}, ReadDataWordMuxM[7:0]}; //lb(u)
|
3'b011: ByteM = ReadDataWordMuxM[31:24];
|
||||||
endcase
|
3'b100: ByteM = ReadDataWordMuxM[39:32];
|
||||||
|
3'b101: ByteM = ReadDataWordMuxM[47:40];
|
||||||
assign offset1 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[15:8]} : {{56{ReadDataWordMuxM[15]}}, ReadDataWordMuxM[15:8]}; //lb(u)
|
3'b110: ByteM = ReadDataWordMuxM[55:48];
|
||||||
|
3'b111: ByteM = ReadDataWordMuxM[63:56];
|
||||||
|
endcase
|
||||||
|
|
||||||
|
// halfword mux
|
||||||
|
always_comb
|
||||||
|
case(MemPAdrM[2:1])
|
||||||
|
2'b00: HalfwordM = ReadDataWordMuxM[15:0];
|
||||||
|
2'b01: HalfwordM = ReadDataWordMuxM[31:16];
|
||||||
|
2'b10: HalfwordM = ReadDataWordMuxM[47:32];
|
||||||
|
2'b11: HalfwordM = ReadDataWordMuxM[63:48];
|
||||||
|
endcase
|
||||||
|
|
||||||
|
logic [31:0] WordM;
|
||||||
|
|
||||||
always_comb
|
always_comb
|
||||||
case(Funct3M[0])
|
case(MemPAdrM[2])
|
||||||
1: offset2 = Funct3M[2] ? {{48'b0}, ReadDataWordMuxM[31:16]} : {{48{ReadDataWordMuxM[31]}}, ReadDataWordMuxM[31:16]};//lh(u)
|
1'b0: WordM = ReadDataWordMuxM[31:0];
|
||||||
0: offset2 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[23:16]} : {{56{ReadDataWordMuxM[23]}}, ReadDataWordMuxM[23:16]};//lb(u)
|
1'b1: WordM = ReadDataWordMuxM[63:32];
|
||||||
endcase
|
endcase
|
||||||
|
|
||||||
assign offset3 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[31:24]} : {{56{ReadDataWordMuxM[31]}}, ReadDataWordMuxM[31:24]};//lb(u)
|
|
||||||
|
|
||||||
|
// sign extension
|
||||||
always_comb
|
always_comb
|
||||||
case(Funct3M[1:0])
|
case(Funct3M)
|
||||||
3: offset4 = Funct3M[2] ? {{32'b0}, ReadDataWordMuxM[63:32]} : {{32{ReadDataWordMuxM[63]}}, ReadDataWordMuxM[63:32]};//ld(u) // unaligned will cause fault.
|
3'b000: ReadDataM = {{56{ByteM[7]}}, ByteM}; // lb
|
||||||
2: offset4 = Funct3M[2] ? {{32'b0}, ReadDataWordMuxM[63:32]} : {{32{ReadDataWordMuxM[63]}}, ReadDataWordMuxM[63:32]};//lw(u)
|
3'b001: ReadDataM = {{48{HalfwordM[15]}}, HalfwordM[15:0]}; // lh
|
||||||
1: offset4 = Funct3M[2] ? {{48'b0}, ReadDataWordMuxM[47:32]} : {{48{ReadDataWordMuxM[47]}}, ReadDataWordMuxM[47:32]};//lh(u)
|
3'b010: ReadDataM = {{32{WordM[31]}}, WordM[31:0]}; // lw
|
||||||
0: offset4 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[39:32]} : {{56{ReadDataWordMuxM[39]}}, ReadDataWordMuxM[39:32]};//lb(u)
|
3'b011: ReadDataM = ReadDataWordMuxM; // ld
|
||||||
endcase
|
3'b100: ReadDataM = {56'b0, ByteM[7:0]}; // lbu
|
||||||
|
3'b101: ReadDataM = {48'b0, HalfwordM[15:0]}; // lhu
|
||||||
assign offset5 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[47:40]} : {{56{ReadDataWordMuxM[47]}}, ReadDataWordMuxM[47:40]};//lb(u)
|
3'b110: ReadDataM = {32'b0, WordM[31:0]}; // lwu
|
||||||
|
default: ReadDataM = ReadDataWordMuxM; // Shouldn't happen
|
||||||
always_comb
|
endcase
|
||||||
case(Funct3M[0])
|
|
||||||
1: offset6 = Funct3M[2] ? {{48'b0}, ReadDataWordMuxM[63:48]} : {{48{ReadDataWordMuxM[63]}}, ReadDataWordMuxM[63:48]};//lh(u)
|
|
||||||
0: offset6 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[55:48]} : {{56{ReadDataWordMuxM[55]}}, ReadDataWordMuxM[55:48]};//lb(u)
|
|
||||||
endcase
|
|
||||||
|
|
||||||
assign offset7 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[63:56]} : {{56{ReadDataWordMuxM[63]}}, ReadDataWordMuxM[63:56]};//lb(u)
|
|
||||||
|
|
||||||
// address mux
|
|
||||||
always_comb
|
|
||||||
case(MemPAdrM[2:0])
|
|
||||||
0: ReadDataM = offset0;
|
|
||||||
1: ReadDataM = offset1;
|
|
||||||
2: ReadDataM = offset2;
|
|
||||||
3: ReadDataM = offset3;
|
|
||||||
4: ReadDataM = offset4;
|
|
||||||
5: ReadDataM = offset5;
|
|
||||||
6: ReadDataM = offset6;
|
|
||||||
7: ReadDataM = offset7;
|
|
||||||
endcase
|
|
||||||
|
|
||||||
end else begin // 32-bit
|
end else begin // 32-bit
|
||||||
// byte mux
|
// byte mux
|
||||||
always_comb
|
always_comb
|
||||||
case(Funct3M[1:0])
|
case(MemPAdrM[1:0])
|
||||||
3: offset0 = ReadDataWordMuxM; //ld illegal
|
2'b00: ByteM = ReadDataWordMuxM[7:0];
|
||||||
2: offset0 = ReadDataWordMuxM[31:0]; //lw
|
2'b01: ByteM = ReadDataWordMuxM[15:8];
|
||||||
1: offset0 = Funct3M[2] ? {{16'b0}, ReadDataWordMuxM[15:0]} : {{16{ReadDataWordMuxM[15]}}, ReadDataWordMuxM[15:0]}; //lh(u)
|
2'b10: ByteM = ReadDataWordMuxM[23:16];
|
||||||
0: offset0 = Funct3M[2] ? {{24'b0}, ReadDataWordMuxM[7:0]} : {{24{ReadDataWordMuxM[7]}}, ReadDataWordMuxM[7:0]}; //lb(u)
|
2'b11: ByteM = ReadDataWordMuxM[31:24];
|
||||||
endcase
|
endcase
|
||||||
|
|
||||||
assign offset1 = Funct3M[2] ? {{24'b0}, ReadDataWordMuxM[15:8]} : {{24{ReadDataWordMuxM[15]}}, ReadDataWordMuxM[15:8]}; //lb(u)
|
// halfword mux
|
||||||
|
|
||||||
always_comb
|
always_comb
|
||||||
case(Funct3M[0])
|
case(MemPAdrM[1])
|
||||||
1: offset2 = Funct3M[2] ? {{16'b0}, ReadDataWordMuxM[31:16]} : {{16{ReadDataWordMuxM[31]}}, ReadDataWordMuxM[31:16]};//lh(u)
|
1'b0: HalfwordM = ReadDataWordMuxM[15:0];
|
||||||
0: offset2 = Funct3M[2] ? {{24'b0}, ReadDataWordMuxM[23:16]} : {{24{ReadDataWordMuxM[23]}}, ReadDataWordMuxM[23:16]};//lb(u)
|
1'b1: HalfwordM = ReadDataWordMuxM[31:16];
|
||||||
endcase
|
endcase
|
||||||
|
|
||||||
assign offset3 = Funct3M[2] ? {{24'b0}, ReadDataWordMuxM[31:24]} : {{24{ReadDataWordMuxM[31]}}, ReadDataWordMuxM[31:24]};//lb(u)
|
// sign extension
|
||||||
|
|
||||||
// address mux
|
|
||||||
always_comb
|
always_comb
|
||||||
case(MemPAdrM[1:0])
|
case(Funct3M)
|
||||||
0: ReadDataM = offset0;
|
3'b000: ReadDataM = {{24{ByteM[7]}}, ByteM}; // lb
|
||||||
1: ReadDataM = offset1;
|
3'b001: ReadDataM = {{16{HalfwordM[15]}}, HalfwordM[15:0]}; // lh
|
||||||
2: ReadDataM = offset2;
|
3'b010: ReadDataM = ReadDataWordMuxM; // lw
|
||||||
3: ReadDataM = offset3;
|
3'b100: ReadDataM = {24'b0, ByteM[7:0]}; // lbu
|
||||||
endcase
|
3'b101: ReadDataM = {16'b0, HalfwordM[15:0]}; // lhu
|
||||||
|
default: ReadDataM = ReadDataWordMuxM;
|
||||||
|
endcase
|
||||||
end
|
end
|
||||||
endgenerate
|
endgenerate
|
||||||
endmodule
|
endmodule
|
||||||
|
|||||||
@ -45,15 +45,14 @@ module hptw
|
|||||||
(* mark_debug = "true" *) output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry
|
(* mark_debug = "true" *) output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry
|
||||||
output logic [`PA_BITS-1:0] HPTWAdr,
|
output logic [`PA_BITS-1:0] HPTWAdr,
|
||||||
output logic HPTWRead, // HPTW requesting to read memory
|
output logic HPTWRead, // HPTW requesting to read memory
|
||||||
output logic [2:0] HPTWSize, // 32 or 64 bit access.
|
output logic [2:0] HPTWSize // 32 or 64 bit access.
|
||||||
output logic WalkerInstrPageFaultF, WalkerLoadPageFaultM,WalkerStorePageFaultM // faults
|
|
||||||
);
|
);
|
||||||
|
|
||||||
typedef enum {L0_ADR, L0_RD,
|
typedef enum {L0_ADR, L0_RD,
|
||||||
L1_ADR, L1_RD,
|
L1_ADR, L1_RD,
|
||||||
L2_ADR, L2_RD,
|
L2_ADR, L2_RD,
|
||||||
L3_ADR, L3_RD,
|
L3_ADR, L3_RD,
|
||||||
LEAF, IDLE, FAULT} statetype; // *** placed outside generate statement to remove synthesis errors
|
LEAF, IDLE} statetype; // *** placed outside generate statement to remove synthesis errors
|
||||||
|
|
||||||
generate
|
generate
|
||||||
if (`MEM_VIRTMEM) begin
|
if (`MEM_VIRTMEM) begin
|
||||||
@ -102,11 +101,6 @@ module hptw
|
|||||||
assign DTLBWriteM = (WalkerState == LEAF) & DTLBWalk;
|
assign DTLBWriteM = (WalkerState == LEAF) & DTLBWalk;
|
||||||
assign ITLBWriteF = (WalkerState == LEAF) & ~DTLBWalk;
|
assign ITLBWriteF = (WalkerState == LEAF) & ~DTLBWalk;
|
||||||
|
|
||||||
// Raise faults. DTLBMiss
|
|
||||||
assign WalkerInstrPageFaultF = (WalkerState == FAULT) & ~DTLBWalk;
|
|
||||||
assign WalkerLoadPageFaultM = (WalkerState == FAULT) & DTLBWalk & ~MemWrite;
|
|
||||||
assign WalkerStorePageFaultM = (WalkerState == FAULT) & DTLBWalk & MemWrite;
|
|
||||||
|
|
||||||
// FSM to track PageType based on the levels of the page table traversed
|
// FSM to track PageType based on the levels of the page table traversed
|
||||||
flopr #(2) PageTypeReg(clk, reset, NextPageType, PageType);
|
flopr #(2) PageTypeReg(clk, reset, NextPageType, PageType);
|
||||||
always_comb
|
always_comb
|
||||||
@ -176,7 +170,6 @@ module hptw
|
|||||||
L2_ADR: if (InitialWalkerState == L2_ADR) NextWalkerState = L2_RD; // first access in SV39
|
L2_ADR: if (InitialWalkerState == L2_ADR) NextWalkerState = L2_RD; // first access in SV39
|
||||||
else if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
|
else if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
|
||||||
else if (ValidNonLeafPTE) NextWalkerState = L2_RD;
|
else if (ValidNonLeafPTE) NextWalkerState = L2_RD;
|
||||||
//else NextWalkerState = FAULT;
|
|
||||||
else NextWalkerState = LEAF;
|
else NextWalkerState = LEAF;
|
||||||
L2_RD: if (DCacheStall) NextWalkerState = L2_RD;
|
L2_RD: if (DCacheStall) NextWalkerState = L2_RD;
|
||||||
else NextWalkerState = L1_ADR;
|
else NextWalkerState = L1_ADR;
|
||||||
@ -186,7 +179,6 @@ module hptw
|
|||||||
L1_ADR: if (InitialWalkerState == L1_ADR) NextWalkerState = L1_RD; // first access in SV32
|
L1_ADR: if (InitialWalkerState == L1_ADR) NextWalkerState = L1_RD; // first access in SV32
|
||||||
else if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
|
else if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
|
||||||
else if (ValidNonLeafPTE) NextWalkerState = L1_RD;
|
else if (ValidNonLeafPTE) NextWalkerState = L1_RD;
|
||||||
//else NextWalkerState = FAULT;
|
|
||||||
else NextWalkerState = LEAF;
|
else NextWalkerState = LEAF;
|
||||||
L1_RD: if (DCacheStall) NextWalkerState = L1_RD;
|
L1_RD: if (DCacheStall) NextWalkerState = L1_RD;
|
||||||
else NextWalkerState = L0_ADR;
|
else NextWalkerState = L0_ADR;
|
||||||
@ -195,17 +187,12 @@ module hptw
|
|||||||
// else NextWalkerState = FAULT;
|
// else NextWalkerState = FAULT;
|
||||||
L0_ADR: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
|
L0_ADR: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
|
||||||
else if (ValidNonLeafPTE) NextWalkerState = L0_RD;
|
else if (ValidNonLeafPTE) NextWalkerState = L0_RD;
|
||||||
//else NextWalkerState = FAULT;
|
|
||||||
else NextWalkerState = LEAF;
|
else NextWalkerState = LEAF;
|
||||||
L0_RD: if (DCacheStall) NextWalkerState = L0_RD;
|
L0_RD: if (DCacheStall) NextWalkerState = L0_RD;
|
||||||
else NextWalkerState = LEAF;
|
else NextWalkerState = LEAF;
|
||||||
// LEVEL0: if (ValidLeafPTE) NextWalkerState = LEAF;
|
// LEVEL0: if (ValidLeafPTE) NextWalkerState = LEAF;
|
||||||
// else NextWalkerState = FAULT;
|
// else NextWalkerState = FAULT;
|
||||||
LEAF: NextWalkerState = IDLE; // updates TLB
|
LEAF: NextWalkerState = IDLE; // updates TLB
|
||||||
/* -----\/----- EXCLUDED -----\/-----
|
|
||||||
FAULT: if (ITLBMissF & AnyCPUReqM) NextWalkerState = FAULT; /// **** BUG: Stays in fault 1 cycle longer than it should.
|
|
||||||
else NextWalkerState = IDLE;
|
|
||||||
-----/\----- EXCLUDED -----/\----- */
|
|
||||||
default: begin
|
default: begin
|
||||||
// synthesis translate_off
|
// synthesis translate_off
|
||||||
$error("Default state in HPTW should be unreachable");
|
$error("Default state in HPTW should be unreachable");
|
||||||
@ -215,7 +202,6 @@ module hptw
|
|||||||
endcase
|
endcase
|
||||||
end else begin // No Virtual memory supported; tie HPTW outputs to 0
|
end else begin // No Virtual memory supported; tie HPTW outputs to 0
|
||||||
assign HPTWRead = 0;
|
assign HPTWRead = 0;
|
||||||
assign WalkerInstrPageFaultF = 0; assign WalkerLoadPageFaultM = 0; assign WalkerStorePageFaultM = 0;
|
|
||||||
assign HPTWAdr = 0;
|
assign HPTWAdr = 0;
|
||||||
assign HPTWSize = 3'b000;
|
assign HPTWSize = 3'b000;
|
||||||
end
|
end
|
||||||
|
|||||||
@ -39,7 +39,7 @@ module privileged (
|
|||||||
output logic [`XLEN-1:0] PrivilegedNextPCM,
|
output logic [`XLEN-1:0] PrivilegedNextPCM,
|
||||||
output logic RetM, TrapM,
|
output logic RetM, TrapM,
|
||||||
output logic ITLBFlushF, DTLBFlushM,
|
output logic ITLBFlushF, DTLBFlushM,
|
||||||
input logic InstrValidM, CommittedM,
|
input logic InstrValidM, LSUStall,
|
||||||
input logic FRegWriteM, LoadStallD,
|
input logic FRegWriteM, LoadStallD,
|
||||||
input logic BPPredDirWrongM,
|
input logic BPPredDirWrongM,
|
||||||
input logic BTBPredPCWrongM,
|
input logic BTBPredPCWrongM,
|
||||||
@ -50,7 +50,6 @@ module privileged (
|
|||||||
input logic DCacheAccess,
|
input logic DCacheAccess,
|
||||||
input logic PrivilegedM,
|
input logic PrivilegedM,
|
||||||
input logic ITLBInstrPageFaultF, DTLBLoadPageFaultM, DTLBStorePageFaultM,
|
input logic ITLBInstrPageFaultF, DTLBLoadPageFaultM, DTLBStorePageFaultM,
|
||||||
input logic WalkerInstrPageFaultF, WalkerLoadPageFaultM, WalkerStorePageFaultM,
|
|
||||||
input logic InstrMisalignedFaultM, IllegalIEUInstrFaultD, IllegalFPUInstrD,
|
input logic InstrMisalignedFaultM, IllegalIEUInstrFaultD, IllegalFPUInstrD,
|
||||||
input logic LoadMisalignedFaultM,
|
input logic LoadMisalignedFaultM,
|
||||||
input logic StoreMisalignedFaultM,
|
input logic StoreMisalignedFaultM,
|
||||||
@ -202,9 +201,9 @@ module privileged (
|
|||||||
// lookup or a improperly formatted page table during walking
|
// lookup or a improperly formatted page table during walking
|
||||||
|
|
||||||
// *** merge these at the lsu level.
|
// *** merge these at the lsu level.
|
||||||
assign InstrPageFaultF = ITLBInstrPageFaultF || WalkerInstrPageFaultF;
|
assign InstrPageFaultF = ITLBInstrPageFaultF;
|
||||||
assign LoadPageFaultM = DTLBLoadPageFaultM || WalkerLoadPageFaultM;
|
assign LoadPageFaultM = DTLBLoadPageFaultM;
|
||||||
assign StorePageFaultM = DTLBStorePageFaultM || WalkerStorePageFaultM;
|
assign StorePageFaultM = DTLBStorePageFaultM;
|
||||||
|
|
||||||
// pipeline fault signals
|
// pipeline fault signals
|
||||||
flopenrc #(2) faultregD(clk, reset, FlushD, ~StallD,
|
flopenrc #(2) faultregD(clk, reset, FlushD, ~StallD,
|
||||||
@ -231,7 +230,7 @@ module privileged (
|
|||||||
.PCM,
|
.PCM,
|
||||||
.InstrMisalignedAdrM, .IEUAdrM,
|
.InstrMisalignedAdrM, .IEUAdrM,
|
||||||
.InstrM,
|
.InstrM,
|
||||||
.InstrValidM, .CommittedM,
|
.InstrValidM, .LSUStall,
|
||||||
.TrapM, .MTrapM, .STrapM, .UTrapM, .RetM,
|
.TrapM, .MTrapM, .STrapM, .UTrapM, .RetM,
|
||||||
.InterruptM,
|
.InterruptM,
|
||||||
.ExceptionM,
|
.ExceptionM,
|
||||||
|
|||||||
@ -41,7 +41,7 @@ module trap (
|
|||||||
input logic [`XLEN-1:0] PCM,
|
input logic [`XLEN-1:0] PCM,
|
||||||
input logic [`XLEN-1:0] InstrMisalignedAdrM, IEUAdrM,
|
input logic [`XLEN-1:0] InstrMisalignedAdrM, IEUAdrM,
|
||||||
input logic [31:0] InstrM,
|
input logic [31:0] InstrM,
|
||||||
input logic InstrValidM, CommittedM,
|
input logic InstrValidM, LSUStall,
|
||||||
output logic TrapM, MTrapM, STrapM, UTrapM, RetM,
|
output logic TrapM, MTrapM, STrapM, UTrapM, RetM,
|
||||||
output logic InterruptM,
|
output logic InterruptM,
|
||||||
output logic ExceptionM,
|
output logic ExceptionM,
|
||||||
@ -61,12 +61,12 @@ module trap (
|
|||||||
// Determine pending enabled interrupts
|
// Determine pending enabled interrupts
|
||||||
// interrupt if any sources are pending
|
// interrupt if any sources are pending
|
||||||
// & with a M stage valid bit to avoid interrupts from interrupt a nonexistent flushed instruction (in the M stage)
|
// & with a M stage valid bit to avoid interrupts from interrupt a nonexistent flushed instruction (in the M stage)
|
||||||
// & with ~CommittedM to make sure MEPC isn't chosen so as to rerun the same instr twice
|
// & with ~LSUStall to make sure MEPC isn't chosen so as to rerun the same instr twice
|
||||||
assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) || STATUS_MIE; // if M ints enabled or lower priv 3.1.9
|
assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) || STATUS_MIE; // if M ints enabled or lower priv 3.1.9
|
||||||
assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) || ((PrivilegeModeW == `S_MODE) && STATUS_SIE); // if in lower priv mode, or if S ints enabled and not in higher priv mode 3.1.9
|
assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) || ((PrivilegeModeW == `S_MODE) && STATUS_SIE); // if in lower priv mode, or if S ints enabled and not in higher priv mode 3.1.9
|
||||||
assign PendingIntsM = ((MIP_REGW & MIE_REGW) & ({12{MIntGlobalEnM}} & 12'h888)) | ((SIP_REGW & SIE_REGW) & ({12{SIntGlobalEnM}} & 12'h222));
|
assign PendingIntsM = ((MIP_REGW & MIE_REGW) & ({12{MIntGlobalEnM}} & 12'h888)) | ((SIP_REGW & SIE_REGW) & ({12{SIntGlobalEnM}} & 12'h222));
|
||||||
assign PendingInterruptM = (|PendingIntsM) & InstrValidM;
|
assign PendingInterruptM = (|PendingIntsM) & InstrValidM;
|
||||||
assign InterruptM = PendingInterruptM & ~CommittedM;
|
assign InterruptM = PendingInterruptM & ~LSUStall; // previously CommittedM. The purpose is to delay an interrupt if the instruction in the memory stage is busy in the LSU. LSUStall directly provides this.
|
||||||
//assign ExceptionM = TrapM;
|
//assign ExceptionM = TrapM;
|
||||||
assign ExceptionM = Exception1M;
|
assign ExceptionM = Exception1M;
|
||||||
// *** as of 7/17/21, the system passes with this definition of ExceptionM as being all traps and fails if ExceptionM = Exception1M
|
// *** as of 7/17/21, the system passes with this definition of ExceptionM as being all traps and fails if ExceptionM = Exception1M
|
||||||
|
|||||||
@ -75,7 +75,6 @@ module wallypipelinedhart (
|
|||||||
logic InstrMisalignedFaultM;
|
logic InstrMisalignedFaultM;
|
||||||
logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD;
|
logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD;
|
||||||
logic ITLBInstrPageFaultF, DTLBLoadPageFaultM, DTLBStorePageFaultM;
|
logic ITLBInstrPageFaultF, DTLBLoadPageFaultM, DTLBStorePageFaultM;
|
||||||
logic WalkerInstrPageFaultF, WalkerLoadPageFaultM, WalkerStorePageFaultM;
|
|
||||||
logic LoadMisalignedFaultM, LoadAccessFaultM;
|
logic LoadMisalignedFaultM, LoadAccessFaultM;
|
||||||
logic StoreMisalignedFaultM, StoreAccessFaultM;
|
logic StoreMisalignedFaultM, StoreAccessFaultM;
|
||||||
logic [`XLEN-1:0] InstrMisalignedAdrM;
|
logic [`XLEN-1:0] InstrMisalignedAdrM;
|
||||||
@ -126,7 +125,6 @@ module wallypipelinedhart (
|
|||||||
(* mark_debug = "true" *) logic [`XLEN-1:0] IEUAdrM;
|
(* mark_debug = "true" *) logic [`XLEN-1:0] IEUAdrM;
|
||||||
(* mark_debug = "true" *) logic [`XLEN-1:0] ReadDataM;
|
(* mark_debug = "true" *) logic [`XLEN-1:0] ReadDataM;
|
||||||
logic [`XLEN-1:0] ReadDataW;
|
logic [`XLEN-1:0] ReadDataW;
|
||||||
logic CommittedM;
|
|
||||||
|
|
||||||
// AHB ifu interface
|
// AHB ifu interface
|
||||||
logic [`PA_BITS-1:0] InstrPAdrF;
|
logic [`PA_BITS-1:0] InstrPAdrF;
|
||||||
@ -135,12 +133,12 @@ module wallypipelinedhart (
|
|||||||
logic InstrAckF;
|
logic InstrAckF;
|
||||||
|
|
||||||
// AHB LSU interface
|
// AHB LSU interface
|
||||||
logic [`PA_BITS-1:0] DCtoAHBPAdrM;
|
logic [`PA_BITS-1:0] LsuBusAdr;
|
||||||
logic DCtoAHBReadM;
|
logic LsuBusRead;
|
||||||
logic DCtoAHBWriteM;
|
logic LsuBusWrite;
|
||||||
logic DCfromAHBAck;
|
logic LsuBusAck;
|
||||||
logic [`XLEN-1:0] DCfromAHBReadData;
|
logic [`XLEN-1:0] LsuBusHRDATA;
|
||||||
logic [`XLEN-1:0] DCtoAHBWriteData;
|
logic [`XLEN-1:0] LsuBusHWDATA;
|
||||||
|
|
||||||
logic BPPredWrongE;
|
logic BPPredWrongE;
|
||||||
logic BPPredDirWrongM;
|
logic BPPredDirWrongM;
|
||||||
@ -149,7 +147,7 @@ module wallypipelinedhart (
|
|||||||
logic BPPredClassNonCFIWrongM;
|
logic BPPredClassNonCFIWrongM;
|
||||||
logic [4:0] InstrClassM;
|
logic [4:0] InstrClassM;
|
||||||
logic InstrAccessFaultF;
|
logic InstrAccessFaultF;
|
||||||
logic [2:0] DCtoAHBSizeM;
|
logic [2:0] LsuBusSize;
|
||||||
|
|
||||||
logic ExceptionM;
|
logic ExceptionM;
|
||||||
logic PendingInterruptM;
|
logic PendingInterruptM;
|
||||||
@ -189,7 +187,7 @@ module wallypipelinedhart (
|
|||||||
.PrivilegeModeW, .PTE, .PageType, .SATP_REGW,
|
.PrivilegeModeW, .PTE, .PageType, .SATP_REGW,
|
||||||
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV,
|
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV,
|
||||||
.STATUS_MPP, .ITLBWriteF, .ITLBFlushF,
|
.STATUS_MPP, .ITLBWriteF, .ITLBFlushF,
|
||||||
.WalkerInstrPageFaultF, .ITLBMissF,
|
.ITLBMissF,
|
||||||
|
|
||||||
// pmp/pma (inside mmu) signals. *** temporarily from AHB bus but eventually replace with internal versions pre H
|
// pmp/pma (inside mmu) signals. *** temporarily from AHB bus but eventually replace with internal versions pre H
|
||||||
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
|
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
|
||||||
@ -241,14 +239,14 @@ module wallypipelinedhart (
|
|||||||
// CPU interface
|
// CPU interface
|
||||||
.MemRWM, .Funct3M, .Funct7M(InstrM[31:25]),
|
.MemRWM, .Funct3M, .Funct7M(InstrM[31:25]),
|
||||||
.AtomicM, .ExceptionM, .PendingInterruptM,
|
.AtomicM, .ExceptionM, .PendingInterruptM,
|
||||||
.CommittedM, .DCacheMiss, .DCacheAccess,
|
.DCacheMiss, .DCacheAccess,
|
||||||
.SquashSCW,
|
.SquashSCW,
|
||||||
//.DataMisalignedM(DataMisalignedM),
|
//.DataMisalignedM(DataMisalignedM),
|
||||||
.IEUAdrE, .IEUAdrM, .WriteDataM,
|
.IEUAdrE, .IEUAdrM, .WriteDataM,
|
||||||
.ReadDataM, .FlushDCacheM,
|
.ReadDataM, .FlushDCacheM,
|
||||||
// connected to ahb (all stay the same)
|
// connected to ahb (all stay the same)
|
||||||
.DCtoAHBPAdrM, .DCtoAHBReadM, .DCtoAHBWriteM, .DCfromAHBAck,
|
.LsuBusAdr, .LsuBusRead, .LsuBusWrite, .LsuBusAck,
|
||||||
.DCfromAHBReadData, .DCtoAHBWriteData, .DCtoAHBSizeM,
|
.LsuBusHRDATA, .LsuBusHWDATA, .LsuBusSize,
|
||||||
|
|
||||||
// connect to csr or privilege and stay the same.
|
// connect to csr or privilege and stay the same.
|
||||||
.PrivilegeModeW, // connects to csr
|
.PrivilegeModeW, // connects to csr
|
||||||
@ -270,8 +268,6 @@ module wallypipelinedhart (
|
|||||||
.StoreAccessFaultM, // connects to privilege
|
.StoreAccessFaultM, // connects to privilege
|
||||||
|
|
||||||
.PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF,
|
.PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF,
|
||||||
.WalkerInstrPageFaultF, .WalkerLoadPageFaultM,
|
|
||||||
.WalkerStorePageFaultM,
|
|
||||||
.LSUStall); // change to LSUStall
|
.LSUStall); // change to LSUStall
|
||||||
|
|
||||||
|
|
||||||
@ -283,10 +279,10 @@ module wallypipelinedhart (
|
|||||||
.InstrPAdrF, // *** rename these to match block diagram
|
.InstrPAdrF, // *** rename these to match block diagram
|
||||||
.InstrReadF, .InstrRData, .InstrAckF,
|
.InstrReadF, .InstrRData, .InstrAckF,
|
||||||
// Signals from Data Cache
|
// Signals from Data Cache
|
||||||
.DCtoAHBPAdrM, .DCtoAHBReadM, .DCtoAHBWriteM, .DCtoAHBWriteData,
|
.LsuBusAdr, .LsuBusRead, .LsuBusWrite, .LsuBusHWDATA,
|
||||||
.DCfromAHBReadData,
|
.LsuBusHRDATA,
|
||||||
.MemSizeM(DCtoAHBSizeM[1:0]), // *** remove
|
.LsuBusSize,
|
||||||
.DCfromAHBAck,
|
.LsuBusAck,
|
||||||
|
|
||||||
.HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn,
|
.HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn,
|
||||||
.HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST,
|
.HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST,
|
||||||
@ -317,13 +313,12 @@ module wallypipelinedhart (
|
|||||||
.InstrM, .CSRReadValW, .PrivilegedNextPCM,
|
.InstrM, .CSRReadValW, .PrivilegedNextPCM,
|
||||||
.RetM, .TrapM,
|
.RetM, .TrapM,
|
||||||
.ITLBFlushF, .DTLBFlushM,
|
.ITLBFlushF, .DTLBFlushM,
|
||||||
.InstrValidM, .CommittedM,
|
.InstrValidM, .LSUStall,
|
||||||
.FRegWriteM, .LoadStallD,
|
.FRegWriteM, .LoadStallD,
|
||||||
.BPPredDirWrongM, .BTBPredPCWrongM,
|
.BPPredDirWrongM, .BTBPredPCWrongM,
|
||||||
.RASPredPCWrongM, .BPPredClassNonCFIWrongM,
|
.RASPredPCWrongM, .BPPredClassNonCFIWrongM,
|
||||||
.InstrClassM, .DCacheMiss, .DCacheAccess, .PrivilegedM,
|
.InstrClassM, .DCacheMiss, .DCacheAccess, .PrivilegedM,
|
||||||
.ITLBInstrPageFaultF, .DTLBLoadPageFaultM, .DTLBStorePageFaultM,
|
.ITLBInstrPageFaultF, .DTLBLoadPageFaultM, .DTLBStorePageFaultM,
|
||||||
.WalkerInstrPageFaultF, .WalkerLoadPageFaultM, .WalkerStorePageFaultM,
|
|
||||||
.InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .IllegalFPUInstrD,
|
.InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .IllegalFPUInstrD,
|
||||||
.LoadMisalignedFaultM, .StoreMisalignedFaultM,
|
.LoadMisalignedFaultM, .StoreMisalignedFaultM,
|
||||||
.TimerIntM, .ExtIntM, .SwIntM,
|
.TimerIntM, .ExtIntM, .SwIntM,
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user