forked from Github_Repos/cvw
Updated coremark_bare testbench for IM
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@ -74,7 +74,7 @@ module testbench();
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memfilename = tests[0];
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$readmemh(memfilename, dut.imem.RAM);
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$readmemh(memfilename, dut.uncore.dtim.RAM);
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for(j=268437829; j < 268566528; j = j+1)
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for(j=26843770; j < 268566528; j = j+1)
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dut.uncore.dtim.RAM[j] = 64'b0;
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// ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.addr";
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// ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.lab";
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