forked from Github_Repos/cvw
changes suggested by ben, hopefully fixing buildroot (which is now not running)
This commit is contained in:
slmnemo
parent
5d34db85b2
commit
e3a7e3e2f3
@ -4,18 +4,18 @@ tvDir=$RISCV/linux-testvectors
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tcpPort=1239
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# QEMU Simulation
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(qemu-system-riscv64 \
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qemu-system-riscv64 \
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-M virt -dtb $imageDir/wally-virt.dtb \
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-nographic \
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-bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \
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-singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on \
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> ./qemu-serial \
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-gdb tcp::$tcpPort -S) \
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& riscv64-unknown-elf-gdb -quiet \
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-ex "set pagination off" \
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-ex "set logging overwrite on" \
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-ex "set logging redirect on" \
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-ex "set confirm off" \
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-ex "target extended-remote :$tcpPort" \
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-ex "maintenance packet Qqemu.PhyMemMode:1" \
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-ex "file $imageDir/vmlinux"
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-singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on
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# > ./qemu-serial \
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# -gdb tcp::$tcpPort -S) \
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# & riscv64-unknown-elf-gdb -quiet \
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# -ex "set pagination off" \
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# -ex "set logging overwrite on" \
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# -ex "set logging redirect on" \
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# -ex "set confirm off" \
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# -ex "target extended-remote :$tcpPort" \
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# -ex "maintenance packet Qqemu.PhyMemMode:1" \
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# -ex "file $imageDir/vmlinux"
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@ -36,7 +36,7 @@ module testbench;
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parameter INSTR_WAVEON = 0; // # of instructions at which to turn on waves in graphical sim
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parameter CHECKPOINT = 0;
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parameter RISCV_DIR = "/opt/riscv";
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parameter NO_IE_MTIME_CHECKPOINT = 0;
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parameter NO_SPOOFING = 0;
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parameter DEBUG_TRACE = 0;
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// Debug Levels
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// 0: don't check against QEMU
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@ -93,7 +93,7 @@ module testbench;
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logic [`XLEN-1:0] ExpectedRegValue``STAGE; \
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logic [`XLEN-1:0] ExpectedIEUAdr``STAGE, ExpectedMemReadData``STAGE, ExpectedMemWriteData``STAGE; \
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string ExpectedCSRArray``STAGE[10:0]; \
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logic [`XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0];
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logic [`XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0]; // *** might be redundant?
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`DECLARE_TRACE_SCANNER_SIGNALS(E)
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`DECLARE_TRACE_SCANNER_SIGNALS(M)
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// M-stage expected values
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@ -216,7 +216,7 @@ module testbench;
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/////////////////////////////// Cache Issue ///////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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logic probe;
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if (NO_IE_MTIME_CHECKPOINT)
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if (NO_SPOOFING)
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assign probe = testbench.dut.core.PCM == 64'hffffffff80200c8c
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& testbench.dut.core.InstrM != 32'h14021273
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& testbench.dut.core.InstrValidM;
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@ -356,7 +356,7 @@ module testbench;
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`INIT_CHECKPOINT_VAL(PC, [`XLEN-1:0]);
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`INIT_CHECKPOINT_VAL(MEDELEG, [`XLEN-1:0]);
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`INIT_CHECKPOINT_VAL(MIDELEG, [`XLEN-1:0]);
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if(!NO_IE_MTIME_CHECKPOINT) begin
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if(!NO_SPOOFING) begin
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`INIT_CHECKPOINT_VAL(MIE, [11:0]);
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`INIT_CHECKPOINT_VAL(MIP, [11:0]);
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end
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@ -393,7 +393,7 @@ module testbench;
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// ========== INITIALIZATION ==========
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initial begin
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if(!NO_IE_MTIME_CHECKPOINT) begin
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if(!NO_SPOOFING) begin
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force `MEIP = 0;
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force `SEIP = 0;
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force `UART_IP = 0;
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@ -403,7 +403,7 @@ module testbench;
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$sformat(linuxImageDir,"%s/buildroot/output/images/",RISCV_DIR);
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if (CHECKPOINT!=0)
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$sformat(checkpointDir,"%s/linux-testvectors/checkpoint%0d/",RISCV_DIR,CHECKPOINT);
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$readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
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$readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem); // *** initialize these using zeroes rather than reading from files, see testbench.sv
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$readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem);
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ProgramAddrMapFile = {linuxImageDir,"disassembly/vmlinux.objdump.addr"};
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ProgramLabelMapFile = {linuxImageDir,"disassembly/vmlinux.objdump.lab"};
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@ -460,7 +460,7 @@ module testbench;
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release `INSTRET;
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end
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// Get the E-stage trace reader ahead of the M-stage trace reader
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matchCountE = $fgets(lineE,traceFileE);
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matchCountE = $fgets(lineE,traceFileE); // *** look at removing?
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end
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///////////////////////////////////////////////////////////////////////////////
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@ -545,16 +545,16 @@ module testbench;
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if(`"STAGE`"=="M") begin \
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// override on special conditions \
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if ((dut.core.lsu.LSUPAdrM == 'h10000002) | (dut.core.lsu.LSUPAdrM == 'h10000005) | (dut.core.lsu.LSUPAdrM == 'h10000006)) begin \
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if(!NO_IE_MTIME_CHECKPOINT) begin \
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$display("%tns, %d instrs: Overwrite UART's LSR in memory stage.", $time, AttemptedInstructionCount); \
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if(!NO_SPOOFING) begin \
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$display("%tns, %d instrs: Overwrite UART's Register in memory stage.", $time, AttemptedInstructionCount); \
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force dut.core.ieu.dp.ReadDataM = ExpectedMemReadDataM; \
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end \
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end else \
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if(!NO_IE_MTIME_CHECKPOINT) \
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if(!NO_SPOOFING) \
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release dut.core.ieu.dp.ReadDataM; \
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if(textM.substr(0,5) == "rdtime") begin \
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//$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW-1); \
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if(!NO_IE_MTIME_CHECKPOINT) \
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if(!NO_SPOOFING) \
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force dut.uncore.clint.clint.MTIME = ExpectedRegValueM; \
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end \
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end \
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@ -631,7 +631,7 @@ module testbench;
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if(~dut.core.StallW) begin
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if(textW.substr(0,5) == "rdtime") begin
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//$display("%tns, %d instrs: Releasing force of MTIME_CLINT.", $time, AttemptedInstructionCount);
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if(!NO_IE_MTIME_CHECKPOINT)
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if(!NO_SPOOFING)
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release dut.uncore.clint.clint.MTIME;
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end
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//if (ExpectedIEUAdrM == 'h10000005) begin
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@ -700,7 +700,7 @@ module testbench;
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"stval": `checkCSR(`CSR_BASE.csrs.csrs.STVAL_REGW)
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"mip": begin
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`checkCSR(`CSR_BASE.csrm.MIP_REGW)
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if(!NO_IE_MTIME_CHECKPOINT) begin
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if(!NO_SPOOFING) begin
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if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & 1<<11) == 0)
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force `MEIP = 0;
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if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & 1<<09) == 0)
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@ -716,7 +716,7 @@ module testbench;
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if (fault == 1) begin
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errorCount +=1;
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$display("processed %0d instructions with %0d warnings", AttemptedInstructionCount, warningCount);
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$stop;
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$stop; $stop;
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end
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end // if (DEBUG_TRACE >= 1)
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end // if (checkInstrW)
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@ -732,7 +732,7 @@ module testbench;
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always @(negedge clk) begin
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if(checkInterruptM) begin
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if((interruptInstrCount+1) == AttemptedInstructionCount) begin
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if(!NO_IE_MTIME_CHECKPOINT) begin
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if(!NO_SPOOFING) begin
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case (interruptCauseVal)
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11: begin
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force `MEIP = 1;
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@ -328,20 +328,20 @@ logic [3:0] dummy;
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// initialize the branch predictor
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if (`BPRED_ENABLED == 1)
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initial begin
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integer adrindex;
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begin
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genvar adrindex;
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// Initializing all zeroes into the branch predictor memory.
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for(adrindex = 0; adrindex < 1024; adrindex++) begin
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initial begin
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force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
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force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
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end
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#1;
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for(adrindex = 0; adrindex < 1024; adrindex++) begin
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release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex];
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release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex];
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end
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end
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end
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endmodule
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module riscvassertions;
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