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Formatting and name changes.

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This commit is contained in:
Ross Thompson 2023-01-19 14:08:42 -06:00
parent 47fdff6488
commit e380fd71ff
2 changed files with 26 additions and 16 deletions
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6
pipelined/src/ifu/ifu.sv
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@ -121,10 +121,10 @@ module ifu (
// Spill Support // Spill Support
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
if(`C_SUPPORTED) begin : SpillSupport if(`C_SUPPORTED) begin : Spill
spillsupport #(`ICACHE) spillsupport(.clk, .reset, .StallD, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF, spill #(`ICACHE) spill(.clk, .reset, .StallD, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF,
.InstrDAPageFaultF, .IFUCacheBusStallD, .ITLBMissF, .PCNextFSpill, .PCFSpill, .SelNextSpillF, .PostSpillInstrRawF, .CompressedF); .InstrDAPageFaultF, .IFUCacheBusStallD, .ITLBMissF, .PCNextFSpill, .PCFSpill, .SelNextSpillF, .PostSpillInstrRawF, .CompressedF);
end else begin : NoSpillSupport end else begin : NoSpill
assign PCNextFSpill = PCNextF; assign PCNextFSpill = PCNextF;
assign PCFSpill = PCF; assign PCFSpill = PCF;
assign PostSpillInstrRawF = InstrRawF; assign PostSpillInstrRawF = InstrRawF;

34
pipelined/src/ifu/spillsupport.sv → pipelined/src/ifu/spill.sv
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// spillsupport.sv *** rename to spill.sv // spill.sv
// //
// Written: Ross Thompson ross1728@gmail.com January 28, 2022 // Written: Ross Thompson ross1728@gmail.com January 28, 2022
// Modified: // Modified:
@ -28,7 +28,7 @@
`include "wally-config.vh" `include "wally-config.vh"
module spillsupport #( module spill #(
parameter CACHE_ENABLED // Changes spill threshold to 1 if there is no cache parameter CACHE_ENABLED // Changes spill threshold to 1 if there is no cache
)(input logic clk, )(input logic clk,
input logic reset, input logic reset,
@ -57,6 +57,10 @@ module spillsupport #(
typedef enum logic [1:0] {STATE_READY, STATE_SPILL} statetype; typedef enum logic [1:0] {STATE_READY, STATE_SPILL} statetype;
(* mark_debug = "true" *) statetype CurrState, NextState; (* mark_debug = "true" *) statetype CurrState, NextState;
////////////////////////////////////////////////////////////////////////////////////////////////////
// PC logic
////////////////////////////////////////////////////////////////////////////////////////////////////
// compute PCF+2 from the raw PC+4 // compute PCF+2 from the raw PC+4
mux2 #(`XLEN) pcplus2mux(.d0({PCF[`XLEN-1:2], 2'b10}), .d1({PCPlus4F, 2'b00}), .s(PCF[1]), .y(PCPlus2F)); mux2 #(`XLEN) pcplus2mux(.d0({PCF[`XLEN-1:2], 2'b10}), .d1({PCPlus4F, 2'b00}), .s(PCF[1]), .y(PCPlus2F));
// select between PCNextF and PCF+2 // select between PCNextF and PCF+2
@ -64,6 +68,11 @@ module spillsupport #(
// select between PCF and PCF+2 // select between PCF and PCF+2
mux2 #(`XLEN) pcspillmux(.d0(PCF), .d1(PCPlus2F), .s(SelSpillF), .y(PCFSpill)); mux2 #(`XLEN) pcspillmux(.d0(PCF), .d1(PCPlus2F), .s(SelSpillF), .y(PCFSpill));
////////////////////////////////////////////////////////////////////////////////////////////////////
// Detect spill
////////////////////////////////////////////////////////////////////////////////////////////////////
assign SpillF = &PCF[$clog2(SPILLTHRESHOLD)+1:1]; assign SpillF = &PCF[$clog2(SPILLTHRESHOLD)+1:1];
assign TakeSpillF = SpillF & ~IFUCacheBusStallD & ~(ITLBMissF | (`HPTW_WRITES_SUPPORTED & InstrDAPageFaultF)); assign TakeSpillF = SpillF & ~IFUCacheBusStallD & ~(ITLBMissF | (`HPTW_WRITES_SUPPORTED & InstrDAPageFaultF));
@ -82,18 +91,19 @@ module spillsupport #(
end end
assign SelSpillF = (CurrState == STATE_SPILL); assign SelSpillF = (CurrState == STATE_SPILL);
assign SelNextSpillF = (CurrState == STATE_READY & TakeSpillF) | assign SelNextSpillF = (CurrState == STATE_READY & TakeSpillF) | (CurrState == STATE_SPILL & IFUCacheBusStallD);
(CurrState == STATE_SPILL & IFUCacheBusStallD); assign SpillSaveF = (CurrState == STATE_READY) & TakeSpillF & ~FlushD;
assign SpillSaveF = (CurrState == STATE_READY) & TakeSpillF;
flopenr #(16) SpillInstrReg(.clk(clk), ////////////////////////////////////////////////////////////////////////////////////////////////////
.en(SpillSaveF & ~FlushD), // Merge spilled instruction
.reset(reset), ////////////////////////////////////////////////////////////////////////////////////////////////////
.d(InstrRawF[15:0]),
.q(InstrFirstHalf)); // save the first 2 bytes
flopenr #(16) SpillInstrReg(clk, reset, SpillSaveF, InstrRawF[15:0], InstrFirstHalf);
// merge together
mux2 #(32) postspillmux(InstrRawF, {InstrRawF[15:0], InstrFirstHalf}, SpillF, PostSpillInstrRawF);
mux2 #(32) postspillmux(.d0(InstrRawF), .d1({InstrRawF[15:0], InstrFirstHalf}), .s(SpillF),
.y(PostSpillInstrRawF));
assign CompressedF = PostSpillInstrRawF[1:0] != 2'b11; assign CompressedF = PostSpillInstrRawF[1:0] != 2'b11;
endmodule endmodule