Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge branch 'cachesim' of https://github.com/AlecVercruysse/cvw into cachesim

Browse Source
This commit is contained in:
Limnanthes Serafini 2023-04-13 16:54:16 -07:00
commit e33721fbe4
4 changed files with 12 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
sim/imperas.ic
View File

@ -30,8 +30,8 @@
--override cpu/ignore_non_leaf_DAU=1
--override cpu/wfi_is_nop=T
--override cpu/misa_Extensions_mask=0x0
#--override cpu/updatePTEA=T
#--override cpu/updatePTED=T
--override cpu/updatePTEA=T
--override cpu/updatePTED=T
--override cpu/Sstc=T
# THIS NEEDS FIXING to 16

2
src/fpu/fdivsqrt/fdivsqrtfsm.sv
View File

@ -110,7 +110,7 @@ module fdivsqrtfsm(
always_ff @(posedge clk) begin
if (reset | FlushE) begin
state <= #1 IDLE;
end else if (IFDivStartE) begin
end else if ((state == IDLE) & IFDivStartE) begin
step <= cycles;
if (SpecialCaseE) state <= #1 DONE;
else state <= #1 BUSY;

6
src/fpu/fdivsqrt/fdivsqrtiter.sv
View File

@ -79,8 +79,8 @@ module fdivsqrtiter(
assign initUM = {~SqrtE, {(`DIVb){1'b0}}};
mux2 #(`DIVb+1) Umux(UNext[`DIVCOPIES-1], initU, IFDivStartE, UMux);
mux2 #(`DIVb+1) UMmux(UMNext[`DIVCOPIES-1], initUM, IFDivStartE, UMMux);
flopen #(`DIVb+1) UReg(clk, IFDivStartE|FDivBusyE, UMux, U[0]);
flopen #(`DIVb+1) UMReg(clk, IFDivStartE|FDivBusyE, UMMux, UM[0]);
flopen #(`DIVb+1) UReg(clk, FDivBusyE, UMux, U[0]);
flopen #(`DIVb+1) UMReg(clk, FDivBusyE, UMMux, UM[0]);
// C register/initialization mux
// Initialize C to -1 for sqrt and -R for division
@ -93,7 +93,7 @@ module fdivsqrtiter(
assign initC = {initCUpper, {`DIVb{1'b0}}};
mux2 #(`DIVb+2) cmux(C[`DIVCOPIES], initC, IFDivStartE, NextC);
flopen #(`DIVb+2) creg(clk, IFDivStartE|FDivBusyE, NextC, C[0]);
flopen #(`DIVb+2) creg(clk, FDivBusyE, NextC, C[0]);
// Divisior register
flopen #(`DIVb) dreg(clk, IFDivStartE, DPreproc, D);

9
testbench/tests.vh
View File

@ -1907,8 +1907,10 @@ string arch64zbs[] = '{
"rv64i_m/privilege/src/WALLY-mie-01.S",
"rv64i_m/privilege/src/WALLY-minfo-01.S",
"rv64i_m/privilege/src/WALLY-misa-01.S",
"rv64i_m/privilege/src/WALLY-mmu-sv39-01.S",
"rv64i_m/privilege/src/WALLY-mmu-sv48-01.S",
// "rv64i_m/privilege/src/WALLY-mmu-sv39-01.S", // run this if SVADU_SUPPORTED = 0
// "rv64i_m/privilege/src/WALLY-mmu-sv48-01.S", // run this if SVADU_SUPPORTED = 0
"rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-01.S", // run this if SVADU_SUPPORTED = 1
"rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S", // run this if SVADU_SUPPORTED = 1
"rv64i_m/privilege/src/WALLY-mtvec-01.S",
"rv64i_m/privilege/src/WALLY-pma-01.S",
"rv64i_m/privilege/src/WALLY-pmp-01.S",
@ -1996,7 +1998,8 @@ string arch64zbs[] = '{
"rv32i_m/privilege/src/WALLY-mie-01.S",
"rv32i_m/privilege/src/WALLY-minfo-01.S",
"rv32i_m/privilege/src/WALLY-misa-01.S",
"rv32i_m/privilege/src/WALLY-mmu-sv32-01.S",
// "rv32i_m/privilege/src/WALLY-mmu-sv32-01.S",
"rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S",
"rv32i_m/privilege/src/WALLY-mtvec-01.S",
"rv32i_m/privilege/src/WALLY-pma-01.S",
"rv32i_m/privilege/src/WALLY-pmp-01.S",