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Clean up unused signals

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This commit is contained in:
David Harris 2022-05-12 14:49:58 +00:00
parent f17501ed8c
commit e2e63ca9a8
11 changed files with 18 additions and 22 deletions
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4
pipelined/src/lsu/atomic.sv
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@ -32,7 +32,7 @@
module atomic ( module atomic (
input logic clk, input logic clk,
input logic reset, FlushW, StallW, input logic reset, StallW,
input logic [`XLEN-1:0] ReadDataM, input logic [`XLEN-1:0] ReadDataM,
input logic [`XLEN-1:0] LSUWriteDataM, input logic [`XLEN-1:0] LSUWriteDataM,
input logic [`PA_BITS-1:0] LSUPAdrM, input logic [`PA_BITS-1:0] LSUPAdrM,
@ -52,7 +52,7 @@ module atomic (
.result(AMOResult)); .result(AMOResult));
mux2 #(`XLEN) wdmux(LSUWriteDataM, AMOResult, LSUAtomicM[1], AMOWriteDataM); mux2 #(`XLEN) wdmux(LSUWriteDataM, AMOResult, LSUAtomicM[1], AMOWriteDataM);
assign MemReadM = PreLSURWM[1] & ~IgnoreRequest; assign MemReadM = PreLSURWM[1] & ~IgnoreRequest;
lrsc lrsc(.clk, .reset, .FlushW, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .LSUPAdrM, lrsc lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .LSUPAdrM,
.SquashSCW, .LSURWM); .SquashSCW, .LSURWM);
endmodule endmodule

2
pipelined/src/lsu/lrsc.sv
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@ -34,7 +34,7 @@
module lrsc module lrsc
( (
input logic clk, reset, input logic clk, reset,
input logic FlushW, StallW, input logic StallW,
input logic MemReadM, input logic MemReadM,
input logic [1:0] PreLSURWM, input logic [1:0] PreLSURWM,
output logic [1:0] LSURWM, output logic [1:0] LSURWM,

2
pipelined/src/lsu/lsu.sv
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@ -251,7 +251,7 @@ module lsu (
// Atomic operations // Atomic operations
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
if (`A_SUPPORTED) begin:atomic if (`A_SUPPORTED) begin:atomic
atomic atomic(.clk, .reset, .FlushW, .StallW, .ReadDataM, .LSUWriteDataM, .LSUPAdrM, atomic atomic(.clk, .reset, .StallW, .ReadDataM, .LSUWriteDataM, .LSUPAdrM,
.LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest, .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest,
.AMOWriteDataM, .SquashSCW, .LSURWM); .AMOWriteDataM, .SquashSCW, .LSURWM);
end else begin:lrsc end else begin:lrsc

1
pipelined/src/mmu/hptw.sv
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@ -61,7 +61,6 @@ module hptw
logic DTLBWalk; // register TLBs translation miss requests logic DTLBWalk; // register TLBs translation miss requests
logic [`PPN_BITS-1:0] BasePageTablePPN; logic [`PPN_BITS-1:0] BasePageTablePPN;
logic [`PPN_BITS-1:0] CurrentPPN; logic [`PPN_BITS-1:0] CurrentPPN;
logic MemWrite;
logic Executable, Writable, Readable, Valid, PTE_U; logic Executable, Writable, Readable, Valid, PTE_U;
logic Misaligned, MegapageMisaligned; logic Misaligned, MegapageMisaligned;
logic ValidPTE, LeafPTE, ValidLeafPTE, ValidNonLeafPTE; logic ValidPTE, LeafPTE, ValidLeafPTE, ValidNonLeafPTE;

2
pipelined/src/muldiv/muldiv.sv
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@ -41,7 +41,6 @@ module muldiv (
output logic [`XLEN-1:0] MDUResultW, output logic [`XLEN-1:0] MDUResultW,
// Divide Done // Divide Done
output logic DivBusyE, output logic DivBusyE,
output logic DivE,
// hazards // hazards
input logic StallM, StallW, FlushM, FlushW, TrapM input logic StallM, StallW, FlushM, FlushW, TrapM
); );
@ -52,6 +51,7 @@ module muldiv (
logic [`XLEN*2-1:0] ProdM; logic [`XLEN*2-1:0] ProdM;
logic DivSignedE; logic DivSignedE;
logic DivE;
logic W64M; logic W64M;
// Multiplier // Multiplier

6
pipelined/src/privileged/csr.sv
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@ -41,7 +41,7 @@ module csr #(parameter
input logic StallE, StallM, StallW, input logic StallE, StallM, StallW,
input logic [31:0] InstrM, input logic [31:0] InstrM,
input logic [`XLEN-1:0] PCM, SrcAM, input logic [`XLEN-1:0] PCM, SrcAM,
input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, wfiM, InterruptM, input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, mretM, sretM, wfiM, InterruptM,
input logic MTimerInt, MExtInt, SExtInt, MSwInt, input logic MTimerInt, MExtInt, SExtInt, MSwInt,
input logic [63:0] MTIME_CLINT, input logic [63:0] MTIME_CLINT,
input logic InstrValidM, FRegWriteM, LoadStallD, input logic InstrValidM, FRegWriteM, LoadStallD,
@ -135,7 +135,7 @@ module csr #(parameter
csri csri(.clk, .reset, .InstrValidNotFlushedM, .StallW, csri csri(.clk, .reset, .InstrValidNotFlushedM, .StallW,
.CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM, .CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM,
.MExtInt, .SExtInt, .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .MTimerInt, .MSwInt,
.MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .MIDELEG_REGW, .IP_REGW_writeable); .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .IP_REGW_writeable);
csrsr csrsr(.clk, .reset, .StallW, csrsr csrsr(.clk, .reset, .StallW,
.WriteMSTATUSM, .WriteMSTATUSHM, .WriteSSTATUSM, .WriteMSTATUSM, .WriteMSTATUSHM, .WriteSSTATUSM,
.TrapM, .FRegWriteM, .NextPrivilegeModeM, .PrivilegeModeW, .TrapM, .FRegWriteM, .NextPrivilegeModeM, .PrivilegeModeW,
@ -145,7 +145,7 @@ module csr #(parameter
.STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TVM, .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TVM,
.STATUS_FS, .BigEndianM); .STATUS_FS, .BigEndianM);
csrc counters(.clk, .reset, csrc counters(.clk, .reset,
.StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW, .StallE, .StallM, .StallW, .FlushM, .FlushW,
.InstrValidM, .LoadStallD, .CSRMWriteM, .InstrValidM, .LoadStallD, .CSRMWriteM,
.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM, .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM,
.InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,

2
pipelined/src/privileged/csrc.sv
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@ -43,7 +43,7 @@ module csrc #(parameter
) ( ) (
input logic clk, reset, input logic clk, reset,
input logic StallE, StallM, StallW, input logic StallE, StallM, StallW,
input logic FlushE, FlushM, FlushW, input logic FlushM, FlushW,
input logic InstrValidM, LoadStallD, CSRMWriteM, input logic InstrValidM, LoadStallD, CSRMWriteM,
input logic BPPredDirWrongM, input logic BPPredDirWrongM,
input logic BTBPredPCWrongM, input logic BTBPredPCWrongM,

1
pipelined/src/privileged/csri.sv
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@ -43,7 +43,6 @@ module csri #(parameter
input logic [`XLEN-1:0] CSRWriteValM, input logic [`XLEN-1:0] CSRWriteValM,
input logic [11:0] CSRAdrM, input logic [11:0] CSRAdrM,
(* mark_debug = "true" *) input logic MExtInt, SExtInt, MTimerInt, MSwInt, (* mark_debug = "true" *) input logic MExtInt, SExtInt, MTimerInt, MSwInt,
input logic [11:0] MIDELEG_REGW,
output logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, output logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW,
(* mark_debug = "true" *) output logic [11:0] IP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0 (* mark_debug = "true" *) output logic [11:0] IP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0
); );

10
pipelined/src/privileged/privileged.sv
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@ -39,7 +39,7 @@ module privileged (
output logic [`XLEN-1:0] PrivilegedNextPCM, output logic [`XLEN-1:0] PrivilegedNextPCM,
output logic RetM, TrapM, output logic RetM, TrapM,
output logic ITLBFlushF, DTLBFlushM, output logic ITLBFlushF, DTLBFlushM,
input logic InstrValidM, CommittedM, DivE, input logic InstrValidM, CommittedM,
input logic FRegWriteM, LoadStallD, input logic FRegWriteM, LoadStallD,
input logic BPPredDirWrongM, input logic BPPredDirWrongM,
input logic BTBPredPCWrongM, input logic BTBPredPCWrongM,
@ -97,7 +97,7 @@ module privileged (
logic InstrAccessFaultD, InstrAccessFaultE, InstrAccessFaultM; logic InstrAccessFaultD, InstrAccessFaultE, InstrAccessFaultM;
logic IllegalInstrFaultM; logic IllegalInstrFaultM;
logic MTrapM, STrapM, UTrapM; logic MTrapM, STrapM;
(* mark_debug = "true" *) logic InterruptM; (* mark_debug = "true" *) logic InterruptM;
logic STATUS_SPP, STATUS_TSR, STATUS_TW, STATUS_TVM; logic STATUS_SPP, STATUS_TSR, STATUS_TW, STATUS_TVM;
@ -158,7 +158,7 @@ module privileged (
.FlushE, .FlushM, .FlushW, .FlushE, .FlushM, .FlushW,
.StallE, .StallM, .StallW, .StallE, .StallM, .StallW,
.InstrM, .PCM, .SrcAM, .InstrM, .PCM, .SrcAM,
.CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .UTrapM, .mretM, .sretM, .wfiM, .InterruptM, .CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .mretM, .sretM, .wfiM, .InterruptM,
.MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTimerInt, .MExtInt, .SExtInt, .MSwInt,
.MTIME_CLINT, .MTIME_CLINT,
.InstrValidM, .FRegWriteM, .LoadStallD, .InstrValidM, .FRegWriteM, .LoadStallD,
@ -225,8 +225,8 @@ module privileged (
.PCM, .PCM,
.IEUAdrM, .IEUAdrM,
.InstrM, .InstrM,
.InstrValidM, .CommittedM, .DivE, .InstrValidM, .CommittedM,
.TrapM, .MTrapM, .STrapM, .UTrapM, .RetM, .TrapM, .MTrapM, .STrapM, .RetM,
.InterruptM, .IntPendingM, .InterruptM, .IntPendingM,
.ExceptionM, .ExceptionM,
.PrivilegedNextPCM, .CauseM, .NextFaultMtvalM); .PrivilegedNextPCM, .CauseM, .NextFaultMtvalM);

5
pipelined/src/privileged/trap.sv
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@ -46,8 +46,8 @@ module trap (
input logic [`XLEN-1:0] PCM, input logic [`XLEN-1:0] PCM,
input logic [`XLEN-1:0] IEUAdrM, input logic [`XLEN-1:0] IEUAdrM,
input logic [31:0] InstrM, input logic [31:0] InstrM,
input logic InstrValidM, CommittedM, DivE, input logic InstrValidM, CommittedM,
output logic TrapM, MTrapM, STrapM, UTrapM, RetM, output logic TrapM, MTrapM, STrapM, RetM,
output logic InterruptM, IntPendingM, output logic InterruptM, IntPendingM,
output logic ExceptionM, output logic ExceptionM,
output logic [`XLEN-1:0] PrivilegedNextPCM, CauseM, NextFaultMtvalM output logic [`XLEN-1:0] PrivilegedNextPCM, CauseM, NextFaultMtvalM
@ -59,7 +59,6 @@ module trap (
(* mark_debug = "true" *) logic [11:0] PendingIntsM, ValidIntsM; (* mark_debug = "true" *) logic [11:0] PendingIntsM, ValidIntsM;
//logic InterruptM; //logic InterruptM;
logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector; logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector;
logic Exception1M;
// Determine pending enabled interrupts // Determine pending enabled interrupts
// interrupt if any sources are pending // interrupt if any sources are pending

5
pipelined/src/wally/wallypipelinedcore.sv
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@ -86,7 +86,6 @@ module wallypipelinedcore (
logic PCSrcE; logic PCSrcE;
logic CSRWritePendingDEM; logic CSRWritePendingDEM;
logic DivBusyE; logic DivBusyE;
logic DivE;
logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD; logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD;
logic SquashSCW; logic SquashSCW;
// floating point unit signals // floating point unit signals
@ -323,7 +322,7 @@ module wallypipelinedcore (
.InstrM, .CSRReadValW, .PrivilegedNextPCM, .InstrM, .CSRReadValW, .PrivilegedNextPCM,
.RetM, .TrapM, .RetM, .TrapM,
.ITLBFlushF, .DTLBFlushM, .ITLBFlushF, .DTLBFlushM,
.InstrValidM, .CommittedM, .DivE, .InstrValidM, .CommittedM,
.FRegWriteM, .LoadStallD, .FRegWriteM, .LoadStallD,
.BPPredDirWrongM, .BTBPredPCWrongM, .BPPredDirWrongM, .BTBPredPCWrongM,
.RASPredPCWrongM, .BPPredClassNonCFIWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM,
@ -360,7 +359,7 @@ module wallypipelinedcore (
.clk, .reset, .clk, .reset,
.ForwardedSrcAE, .ForwardedSrcBE, .ForwardedSrcAE, .ForwardedSrcBE,
.Funct3E, .Funct3M, .MDUE, .W64E, .Funct3E, .Funct3M, .MDUE, .W64E,
.MDUResultW, .DivBusyE, .DivE, .MDUResultW, .DivBusyE,
.StallM, .StallW, .FlushM, .FlushW, .TrapM .StallM, .StallW, .FlushM, .FlushW, .TrapM
); );
end else begin // no M instructions supported end else begin // no M instructions supported