forked from Github_Repos/cvw
fdivsqrt cleanup
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@ -50,7 +50,7 @@ module fdivsqrtpreproc (
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output logic [`XLEN-1:0] AM
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output logic [`XLEN-1:0] AM
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);
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);
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logic [`DIVb-1:0] XPreproc, DPreproc;
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logic [`DIVb-1:0] Xfract, Dfract;
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logic [`DIVb:0] PreSqrtX;
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logic [`DIVb:0] PreSqrtX;
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logic [`DIVb+3:0] DivX, DivXShifted, SqrtX, PreShiftX; // Variations of dividend, to be muxed
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logic [`DIVb+3:0] DivX, DivXShifted, SqrtX, PreShiftX; // Variations of dividend, to be muxed
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logic [`NE+1:0] QeE; // Quotient Exponent (FP only)
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logic [`NE+1:0] QeE; // Quotient Exponent (FP only)
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@ -111,8 +111,8 @@ module fdivsqrtpreproc (
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lzc #(`DIVb) lzcY (IFD, mE);
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lzc #(`DIVb) lzcY (IFD, mE);
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// Normalization shift: shift off leading one
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// Normalization shift: shift off leading one
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assign XPreproc = (IFX << ell) << 1;
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assign Xfract = (IFX << ell) << 1;
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assign DPreproc = (IFD << mE) << 1;
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assign Dfract = (IFD << mE) << 1;
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// *** CT: move to fdivsqrtintpreshift
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// *** CT: move to fdivsqrtintpreshift
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@ -154,6 +154,8 @@ module fdivsqrtpreproc (
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assign ISpecialCaseE = 0;
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assign ISpecialCaseE = 0;
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end
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end
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// CT *** fdivsqrtfplead1
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//////////////////////////////////////////////////////
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//////////////////////////////////////////////////////
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// Floating-Point Preprocessing
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// Floating-Point Preprocessing
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// append leading 1 (for nonzero inputs)
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// append leading 1 (for nonzero inputs)
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@ -162,10 +164,10 @@ module fdivsqrtpreproc (
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// Denormalized numbers have Xe = 0 and an unbiased exponent of 1-BIAS. They are shifted right if the number of leading zeros is odd.
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// Denormalized numbers have Xe = 0 and an unbiased exponent of 1-BIAS. They are shifted right if the number of leading zeros is odd.
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//////////////////////////////////////////////////////
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//////////////////////////////////////////////////////
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assign DivX = {3'b000, ~NumerZeroE, XPreproc};
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assign DivX = {3'b000, ~NumerZeroE, Xfract};
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// Sqrt is initialized on step one as R(X-1), so depends on Radix
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// Sqrt is initialized on step one as R(X-1), so depends on Radix
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mux2 #(`DIVb+1) sqrtxmux({~XZeroE, XPreproc}, {1'b0, ~XZeroE, XPreproc[`DIVb-1:1]}, (Xe[0] ^ ell[0]), PreSqrtX);
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mux2 #(`DIVb+1) sqrtxmux({~XZeroE, Xfract}, {1'b0, ~XZeroE, Xfract[`DIVb-1:1]}, (Xe[0] ^ ell[0]), PreSqrtX);
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if (`RADIX == 2) assign SqrtX = {3'b111, PreSqrtX};
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if (`RADIX == 2) assign SqrtX = {3'b111, PreSqrtX};
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else assign SqrtX = {2'b11, PreSqrtX, 1'b0};
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else assign SqrtX = {2'b11, PreSqrtX, 1'b0};
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mux2 #(`DIVb+4) prexmux(DivX, SqrtX, SqrtE, PreShiftX);
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mux2 #(`DIVb+4) prexmux(DivX, SqrtX, SqrtE, PreShiftX);
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@ -181,7 +183,7 @@ module fdivsqrtpreproc (
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end
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end
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// Divisior register
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// Divisior register
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flopen #(`DIVb+4) dreg(clk, IFDivStartE, {4'b0001, DPreproc}, D);
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flopen #(`DIVb+4) dreg(clk, IFDivStartE, {4'b0001, Dfract}, D);
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// Floating-point exponent
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// Floating-point exponent
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fdivsqrtexpcalc expcalc(.Fmt(FmtE), .Xe, .Ye, .Sqrt(SqrtE), .XZero(XZeroE), .ell, .m(mE), .Qe(QeE));
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fdivsqrtexpcalc expcalc(.Fmt(FmtE), .Xe, .Ye, .Sqrt(SqrtE), .XZero(XZeroE), .ell, .m(mE), .Qe(QeE));
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