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fixed upper bits page fault signal

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This commit is contained in:
Kip Macsai-Goren 2021-07-06 18:32:47 -04:00
parent 2e2aa2a972
commit e08a578908
1 changed files with 4 additions and 6 deletions
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10
wally-pipelined/src/mmu/tlbcontrol.sv
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@ -70,12 +70,10 @@ module tlbcontrol #(parameter TLB_ENTRIES = 8,
if (`XLEN==64) begin if (`XLEN==64) begin
assign SV39Mode = (SVMode == `SV39); assign SV39Mode = (SVMode == `SV39);
// generate page fault if upper bits aren't all the same // generate page fault if upper bits aren't all the same
logic UpperOnes39, UpperZeros39, UpperOnes48, UpperZeros48; logic UpperEqual39, UpperEqual48;
assign UpperOnes39 = &(Address[63:39]); assign UpperEqual39 = &(Address[63:38]) | ~|(Address[63:38]);
assign UpperZeros39 = ~|(Address[63:39]); assign UpperEqual48 = &(Address[63:47]) | ~|(Address[63:47]);
assign UpperOnes48 = &(Address[63:48]); assign UpperBitsUnequalPageFault = SvMode ? ~UpperEqual39 : ~UpperEqual48;
assign UpperZeros48 = ~|(Address[63:48]);
assign UpperBitsUnequalPageFault = SV39Mode ? (Address[38] ? UpperOnes39 : UpperZeros39) : (Address[47] ? UpperOnes48 : UpperZeros48);
end else begin end else begin
assign SV39Mode = 0; assign SV39Mode = 0;
assign UpperBitsUnequalPageFault = 0; assign UpperBitsUnequalPageFault = 0;