forked from Github_Repos/cvw
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
This commit is contained in:
Kip Macsai-Goren
commit
dfff318060
4
.gitignore
vendored
4
.gitignore
vendored
@ -16,8 +16,8 @@ wlft*
|
||||
/imperas-riscv-tests/FunctionRadix.addr
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/imperas-riscv-tests/ProgramMap.txt
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/imperas-riscv-tests/logs
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||||
/wally-pipelined/busybear-testgen/gdbcombined.txt
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||||
/wally-pipelined/busybear-testgen/first10.txt
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/wally-pipelined/linux-testgen/qemu_output.txt
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/wally-pipelined/linux-testgen/qemu_in_gdb_format.txt
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||||
*.o
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*.d
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testsBP/*/*/*.elf*
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@ -2,25 +2,26 @@
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# Uncomment this version for GDB/QEMU debugging
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||||
# - Opens up GDB interactively
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# - Logs raw QEMU output to qemu_output.txt
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#(qemu-system-riscv64 -M virt -nographic -bios /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/fw_jump.elf -kernel /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/Image -append "root=/dev/vda ro" -initrd /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -s -S 2> /mnt/scratch/wally_linux_output/qemu_output.txt) & riscv64-unknown-elf-gdb
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#(qemu-system-riscv64 -M virt -nographic -bios /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/fw_jump.elf -kernel /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/Image -append "root=/dev/vda ro" -initrd /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -s -S 2> qemu_output.txt) & riscv64-unknown-elf-gdb
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# Uncomment this version to generate qemu_output.txt
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# - Uses GDB script
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# - Logs raw QEMU output to qemu_output.txt
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#(qemu-system-riscv64 -M virt -nographic -bios /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/fw_jump.elf -kernel /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/Image -append "root=/dev/vda ro" -initrd /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -s -S 2>/mnt/scratch/wally_linux_output/qemu_output.txt) & riscv64-unknown-elf-gdb -x gdbinit_qemulog
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#(qemu-system-riscv64 -M virt -nographic -bios /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/fw_jump.elf -kernel /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/Image -append "root=/dev/vda ro" -initrd /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -s -S 2>qemu_output.txt) & riscv64-unknown-elf-gdb -x gdbinit_qemulog_debug
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# Uncomment this version for parse_qemu.py debugging
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# - Uses qemu_output.txt
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# - Makes qemu_in_gdb_format.txt
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# - Logs parse_qemu.py's simulated gdb output to qemu_in_gdb_format.txt
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#cat /mnt/scratch/wally_linux_output/qemu_output.txt | ./parse_qemu.py >/mnt/scratch/wally_linux_output/qemu_in_gdb_format.txt
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#cat qemu_output.txt | ./parse_qemu.py >qemu_in_gdb_format.txt
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#cat qemu_output.txt | ./parse_qemu.py | ./parse_gdb_output.py "/courses/e190ax/buildroot_boot/"
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# Uncomment this version for parse_gdb_output.py debugging
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# - Uses qemu_in_gdb_format.txt
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# - Logs info needed by buildroot testbench
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cat /mnt/scratch/wally_linux_output/qemu_in_gdb_format.txt | ./parse_gdb_output.py "/courses/e190ax/buildroot_boot/"
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#cat qemu_in_gdb_format.txt | ./parse_gdb_output.py "/courses/e190ax/buildroot_boot/"
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# =========== Just Do the Thing ==========
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# Uncomment this version for the whole thing (if it works ha ha_
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# Uncomment this version for the whole thing
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# - Logs info needed by buildroot testbench
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#(qemu-system-riscv64 -M virt -nographic -bios /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/fw_jump.elf -kernel /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/Image -append "root=/dev/vda ro" -initrd /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -s -S 2>&1 >/dev/null | pv -l | ./parse_qemu.py | ./parse_gdb_output.py "/courses/e190ax/buildroot_boot/") & riscv64-unknown-elf-gdb -x gdbinit_qemulog
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(qemu-system-riscv64 -M virt -nographic -bios /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/fw_jump.elf -kernel /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/Image -append "root=/dev/vda ro" -initrd /courses/e190ax/qemu_sim/rv64_initrd/buildroot_experimental/output/images/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -s -S 2>&1 >/dev/null | pv -l | ./parse_qemu.py | ./parse_gdb_output.py "/courses/e190ax/buildroot_boot/") & riscv64-unknown-elf-gdb -x gdbinit_qemulog
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@ -27,7 +27,7 @@ try:
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readType = ''
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lastReadType = ''
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readLoc = ''
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instrStart = -1
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lineOffset = -1
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lastRegs = ''
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curRegs = ''
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storeReg = ''
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@ -40,10 +40,12 @@ try:
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for l in fileinput.input('-'):
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l = l.split("#")[0].rstrip()
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if l.startswith('=>'):
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# Begin new instruction
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instrs += 1
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storeAMO = ''
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if instrs % 10000 == 0:
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print(instrs)
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# Instr in human assembly
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wPC.write('{} ***\n'.format(' '.join(l.split(':')[1].split()[0:2])))
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if '\tld' in l or '\tlw' in l or '\tlh' in l or '\tlb' in l:
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currentRead = l.split()[-1].split(',')[0]
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@ -53,7 +55,6 @@ try:
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readLoc = l.split()[-1].split(',')[1].split('(')[1][:-1]
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readType = l.split()[-2]
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if 'amo' in l:
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#print(l)
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currentRead = l.split()[-1].split(',')[0]
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readOffset = "0"
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readLoc = l.split()[-1].split('(')[1][:-1]
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@ -63,7 +64,6 @@ try:
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storeReg = l.split()[-1].split(',')[1]
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storeAMO = l.split()[-2]
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if '\tsd' in l or '\tsw' in l or '\tsh' in l or '\tsb' in l:
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#print(l)
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s = l.split('#')[0].split()[-1]
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storeReg = s.split(',')[0]
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if len(s.split(',')) < 2:
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@ -74,17 +74,19 @@ try:
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print(l)
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storeOffset = s.split(',')[1].split('(')[0]
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storeLoc = s.split(',')[1].split('(')[1][:-1]
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instrStart = 0
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elif instrStart != -1:
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instrStart += 1
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if instrStart == 1:
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lineOffset = 0
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elif lineOffset != -1:
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||||
lineOffset += 1
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if lineOffset == 1:
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# Instr in hex comes one line after the instruction
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wPC.write('{}\n'.format(l.split()[-1][2:]))
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elif instrStart < 34:
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# As well as instr address
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wPC.write('{}\n'.format(l.split()[0][2:].strip(":")))
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elif lineOffset <= (1+32):
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# Next 32 lines are the Register File
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if lastRead == l.split()[0]:
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readData = int(l.split()[1][2:], 16)
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readData <<= (8 * (lastReadLoc % 8))
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#if(lastReadLoc % 8 != 0 and ('lw' in lastReadType or 'lb' in lastReadType)):
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# readData <<= 32
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wMem.write('{:x}\n'.format(readData))
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if readLoc == l.split()[0]:
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readLoc = l.split()[1][2:]
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@ -92,16 +94,12 @@ try:
|
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storeReg = l.split()[1]
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if storeLoc == l.split()[0]:
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storeLoc = l.split()[1][2:]
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if instrStart > 2:
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#print(l)
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#print(instrStart)
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if lineOffset > (1+1):
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# Start logging x1 onwards (we don't care about x0)
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curRegs += '{}\n'.format(l.split()[1][2:])
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elif instrStart < 35:
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#print("----------")
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#print(l.split()[1][2:])
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wPC.write('{}\n'.format(l.split()[1][2:]))
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#print(l.split()[1][2:])
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if any([c == l.split()[0] for c in csrs]):
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#elif "pc" in l:
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# wPC.write('{}\n'.format(l.split()[1][2:]))
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if any([csr == l.split()[0] for csr in csrs]):
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if l.split()[0] in curCSRs:
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if curCSRs[l.split()[0]] != l.split()[1]:
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if firstCSR:
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@ -112,51 +110,53 @@ try:
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wCSRs.write('{}\n{}\n'.format(l.split()[0], l.split()[1][2:]))
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curCSRs[l.split()[0]] = l.split()[1]
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if '-----' in l: # end of each cycle
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if curRegs != lastRegs:
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if lastRegs == '':
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wReg.write(curRegs)
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else:
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for i in range(32):
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if curRegs.split('\n')[i] != lastRegs.split('\n')[i]:
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wReg.write('{}\n'.format(i+1))
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wReg.write('{}\n'.format(curRegs.split('\n')[i]))
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break
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lastRegs = curRegs
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if lastAMO != '':
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if 'amoadd' in lastAMO:
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lastStoreReg = hex(int(lastStoreReg[2:], 16) + readData)[2:]
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elif 'amoand' in lastAMO:
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lastStoreReg = hex(int(lastStoreReg[2:], 16) & readData)[2:]
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elif 'amoor' in lastAMO:
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lastStoreReg = hex(int(lastStoreReg[2:], 16) | readData)[2:]
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elif 'amoswap' in lastAMO:
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lastStoreReg = hex(int(lastStoreReg[2:], 16))[2:]
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else:
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print(lastAMO)
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exit()
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wMemW.write('{}\n'.format(lastStoreReg))
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wMemW.write('{:x}\n'.format(int(lastStoreLoc, 16)))
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if storeReg != '' and storeOffset != '' and storeLoc != '' and storeAMO == '':
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storeLocOffset = int(storeOffset,10) + int(storeLoc, 16)
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#wMemW.write('{:x}\n'.format(int(storeReg, 16) << (8 * (storeLocOffset % 8))))
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wMemW.write('{}\n'.format(storeReg[2:]))
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wMemW.write('{:x}\n'.format(storeLocOffset))
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if readOffset != '' and readLoc != '':
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||||
wMem.write('{:x}\n'.format(int(readOffset,10) + int(readLoc, 16)))
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lastReadLoc = int(readOffset,10) + int(readLoc, 16)
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lastReadType = readType
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readOffset = ''
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||||
readLoc = ''
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curRegs = ''
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||||
instrStart = -1
|
||||
lastRead = currentRead
|
||||
currentRead = ''
|
||||
lastStoreReg = storeReg
|
||||
lastStoreLoc = storeLoc
|
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storeReg = ''
|
||||
storeOffset = ''
|
||||
storeLoc = ''
|
||||
lastAMO = storeAMO
|
||||
if curRegs != lastRegs:
|
||||
if lastRegs == '':
|
||||
wReg.write(curRegs)
|
||||
else:
|
||||
for i in range(32):
|
||||
if curRegs.split('\n')[i] != lastRegs.split('\n')[i]:
|
||||
wReg.write('{}\n'.format(i+1))
|
||||
wReg.write('{}\n'.format(curRegs.split('\n')[i]))
|
||||
break
|
||||
lastRegs = curRegs
|
||||
if lastAMO != '':
|
||||
if 'amoadd' in lastAMO:
|
||||
lastStoreReg = hex(int(lastStoreReg[2:], 16) + readData)[2:]
|
||||
elif 'amoand' in lastAMO:
|
||||
lastStoreReg = hex(int(lastStoreReg[2:], 16) & readData)[2:]
|
||||
elif 'amoor' in lastAMO:
|
||||
lastStoreReg = hex(int(lastStoreReg[2:], 16) | readData)[2:]
|
||||
elif 'amoswap' in lastAMO:
|
||||
lastStoreReg = hex(int(lastStoreReg[2:], 16))[2:]
|
||||
else:
|
||||
print(lastAMO)
|
||||
exit()
|
||||
#print('lastStoreReg {}\n'.format(lastStoreReg))
|
||||
#print('lastStoreLoc '+str(lastStoreLoc))
|
||||
wMemW.write('{}\n'.format(lastStoreReg))
|
||||
wMemW.write('{:x}\n'.format(int(lastStoreLoc, 16)))
|
||||
if storeReg != '' and storeOffset != '' and storeLoc != '' and storeAMO == '':
|
||||
storeLocOffset = int(storeOffset,10) + int(storeLoc, 16)
|
||||
#wMemW.write('{:x}\n'.format(int(storeReg, 16) << (8 * (storeLocOffset % 8))))
|
||||
wMemW.write('{}\n'.format(storeReg[2:]))
|
||||
wMemW.write('{:x}\n'.format(storeLocOffset))
|
||||
if readOffset != '' and readLoc != '':
|
||||
wMem.write('{:x}\n'.format(int(readOffset,10) + int(readLoc, 16)))
|
||||
lastReadLoc = int(readOffset,10) + int(readLoc, 16)
|
||||
lastReadType = readType
|
||||
readOffset = ''
|
||||
readLoc = ''
|
||||
curRegs = ''
|
||||
lineOffset = -1
|
||||
lastRead = currentRead
|
||||
currentRead = ''
|
||||
lastStoreReg = storeReg
|
||||
lastStoreLoc = storeLoc
|
||||
storeReg = ''
|
||||
storeOffset = ''
|
||||
storeLoc = ''
|
||||
lastAMO = storeAMO
|
||||
|
||||
|
||||
except (FileNotFoundError):
|
||||
|
||||
@ -39,12 +39,14 @@ def parseCSRs(l):
|
||||
csr = l.split()[0]
|
||||
val = int(l.split()[1],16)
|
||||
if inPageFault:
|
||||
if l.startswith("mstatus") or l.startswith("mepc") or l.startswith("mcause") or l.startswith("mtval") or l.startswith("sepc") or l.startswith("scause") or l.startswith("stval"):
|
||||
# We do update some CSRs
|
||||
CSRs[csr] = val
|
||||
else:
|
||||
# Others we preserve until changed later
|
||||
pageFaultCSRs[csr] = val
|
||||
# Not sure if these CSRs should be updated or not during page fault.
|
||||
#if l.startswith("mstatus") or l.startswith("mepc") or l.startswith("mcause") or l.startswith("mtval") or l.startswith("sepc") or l.startswith("scause") or l.startswith("stval"):
|
||||
# # We do update some CSRs
|
||||
# CSRs[csr] = val
|
||||
#else:
|
||||
# # Others we preserve until changed later
|
||||
# pageFaultCSRs[csr] = val
|
||||
pageFaultCSRs[csr] = val
|
||||
elif pageFaultCSRs and (csr in pageFaultCSRs):
|
||||
if (val != pageFaultCSRs[csr]):
|
||||
del pageFaultCSRs[csr]
|
||||
|
||||
@ -35,7 +35,7 @@ vopt +acc work.testbench -o workopt
|
||||
|
||||
vsim workopt -suppress 8852,12070
|
||||
|
||||
do ./wave-dos/busybear-waves.do
|
||||
do ./wave-dos/linux-waves.do
|
||||
|
||||
#-- Run the Simulation
|
||||
run -all
|
||||
|
||||
@ -35,7 +35,7 @@ vopt +acc work.testbench -o workopt
|
||||
|
||||
vsim workopt -suppress 8852,12070
|
||||
|
||||
do ./wave-dos/bens-busybear-waves.do
|
||||
do ./wave-dos/linux-waves.do
|
||||
|
||||
|
||||
#-- Run the Simulation
|
||||
|
||||
@ -1,64 +0,0 @@
|
||||
# busybear-waves.do
|
||||
restart -f
|
||||
delete wave /*
|
||||
view wave
|
||||
|
||||
add wave /testbench/dut/hart/DataStall
|
||||
add wave /testbench/dut/hart/ICacheStallF
|
||||
add wave /testbench/dut/hart/StallF
|
||||
add wave /testbench/dut/hart/StallD
|
||||
add wave /testbench/dut/hart/StallE
|
||||
add wave /testbench/dut/hart/StallM
|
||||
add wave /testbench/dut/hart/StallW
|
||||
add wave /testbench/dut/hart/FlushD
|
||||
add wave /testbench/dut/hart/FlushE
|
||||
add wave /testbench/dut/hart/FlushM
|
||||
add wave /testbench/dut/hart/FlushW
|
||||
add wave -divider
|
||||
|
||||
add wave /testbench/clk
|
||||
add wave /testbench/reset
|
||||
add wave -divider
|
||||
|
||||
add wave -hex /testbench/dut/hart/ifu/PCF
|
||||
add wave -hex /testbench/PCtext
|
||||
add wave -hex /testbench/pcExpected
|
||||
add wave -hex /testbench/dut/hart/ifu/PCD
|
||||
add wave -hex /testbench/dut/hart/ifu/InstrD
|
||||
add wave /testbench/InstrDName
|
||||
add wave -divider
|
||||
add wave -hex /testbench/dut/hart/ifu/PCE
|
||||
add wave -hex /testbench/dut/hart/ifu/InstrE
|
||||
add wave /testbench/InstrEName
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/SrcAE
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/SrcBE
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE
|
||||
#add wave /testbench/dut/hart/ieu/dp/PCSrcE
|
||||
add wave -divider
|
||||
add wave -hex /testbench/dut/hart/ifu/PCM
|
||||
add wave -hex /testbench/dut/hart/ifu/InstrM
|
||||
add wave /testbench/InstrMName
|
||||
add wave /testbench/dut/uncore/dtim/memwrite
|
||||
add wave -hex /testbench/dut/uncore/HADDR
|
||||
add wave -hex /testbench/dut/uncore/HWDATA
|
||||
add wave -divider
|
||||
add wave -hex /testbench/PCW
|
||||
add wave -hex /testbench/InstrW
|
||||
add wave /testbench/InstrWName
|
||||
add wave /testbench/dut/hart/ieu/dp/RegWriteW
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/ResultW
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/RdW
|
||||
add wave -divider
|
||||
|
||||
# appearance
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {100 ps}
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 150
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
set DefaultRadix hexadecimal
|
||||
@ -1,58 +1,66 @@
|
||||
# busybear-waves.do
|
||||
|
||||
# linux-waves.do
|
||||
restart -f
|
||||
delete wave /*
|
||||
view wave
|
||||
|
||||
-- display input and output signals as hexidecimal values
|
||||
# Diplays All Signals recursively
|
||||
add wave -divider
|
||||
add wave /testbench/clk
|
||||
add wave /testbench/reset
|
||||
add wave -divider
|
||||
add wave -hex /testbench/PCtext
|
||||
|
||||
add wave -divider Stalls_and_Flushes
|
||||
add wave /testbench/dut/hart/StallF
|
||||
add wave /testbench/dut/hart/StallD
|
||||
add wave /testbench/dut/hart/StallE
|
||||
add wave /testbench/dut/hart/StallM
|
||||
add wave /testbench/dut/hart/StallW
|
||||
add wave -group stall_srcs /testbench/dut/hart/DataStall
|
||||
add wave -group stall_srcs /testbench/dut/hart/ICacheStallF
|
||||
add wave /testbench/dut/hart/FlushD
|
||||
add wave /testbench/dut/hart/FlushE
|
||||
add wave /testbench/dut/hart/FlushM
|
||||
add wave /testbench/dut/hart/FlushW
|
||||
|
||||
add wave -divider F
|
||||
add wave -hex /testbench/dut/hart/ifu/PCF
|
||||
add wave -divider D
|
||||
add wave -hex /testbench/pcExpected
|
||||
add wave -hex /testbench/dut/hart/ifu/PCD
|
||||
add wave -hex /testbench/PCtextD
|
||||
add wave /testbench/InstrDName
|
||||
add wave -hex /testbench/dut/hart/ifu/InstrD
|
||||
add wave -hex /testbench/dut/hart/ifu/StallD
|
||||
add wave -hex /testbench/dut/hart/ifu/FlushD
|
||||
add wave -hex /testbench/dut/hart/ifu/StallE
|
||||
add wave -hex /testbench/dut/hart/ifu/FlushE
|
||||
add wave -hex /testbench/dut/hart/ifu/InstrRawD
|
||||
add wave /testbench/CheckInstrD
|
||||
add wave /testbench/lastCheckInstrD
|
||||
add wave /testbench/speculative
|
||||
add wave /testbench/lastPC2
|
||||
add wave -divider
|
||||
add wave -divider
|
||||
add wave /testbench/dut/uncore/HSELBootTim
|
||||
add wave /testbench/dut/uncore/HSELTim
|
||||
add wave /testbench/dut/uncore/HREADTim
|
||||
add wave /testbench/dut/uncore/dtim/HREADTim0
|
||||
add wave /testbench/dut/uncore/HREADYTim
|
||||
add wave -divider
|
||||
add wave /testbench/dut/uncore/HREADBootTim
|
||||
add wave /testbench/dut/uncore/bootdtim/HREADTim0
|
||||
add wave /testbench/dut/uncore/HREADYBootTim
|
||||
add wave /testbench/dut/uncore/HADDR
|
||||
add wave /testbench/dut/uncore/HRESP
|
||||
add wave /testbench/dut/uncore/HREADY
|
||||
add wave /testbench/dut/uncore/HRDATA
|
||||
#add wave -hex /testbench/dut/hart/priv/csr/MTVEC_REG
|
||||
#add wave -hex /testbench/dut/hart/priv/csr/MSTATUS_REG
|
||||
#add wave -hex /testbench/dut/hart/priv/csr/SCOUNTEREN_REG
|
||||
#add wave -hex /testbench/dut/hart/priv/csr/MIE_REG
|
||||
#add wave -hex /testbench/dut/hart/priv/csr/MIDELEG_REG
|
||||
#add wave -hex /testbench/dut/hart/priv/csr/MEDELEG_REG
|
||||
add wave -divider
|
||||
# registers!
|
||||
add wave -hex /testbench/dut/hart/ieu/c/InstrValidD
|
||||
add wave -divider E
|
||||
add wave -hex /testbench/dut/hart/ifu/PCE
|
||||
add wave -hex /testbench/PCtextE
|
||||
add wave /testbench/InstrEName
|
||||
add wave -hex /testbench/dut/hart/ifu/InstrE
|
||||
add wave -hex /testbench/dut/hart/ieu/c/InstrValidE
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/SrcAE
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/SrcBE
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE
|
||||
add wave -divider M
|
||||
add wave -hex /testbench/dut/hart/ifu/PCM
|
||||
add wave -hex /testbench/PCtextM
|
||||
add wave /testbench/InstrMName
|
||||
add wave -hex /testbench/dut/hart/ifu/InstrM
|
||||
add wave -hex /testbench/dut/hart/ieu/c/InstrValidM
|
||||
add wave /testbench/dut/uncore/dtim/memwrite
|
||||
add wave -hex /testbench/dut/uncore/HADDR
|
||||
add wave -hex /testbench/HWRITE
|
||||
add wave -hex /testbench/dut/uncore/HWDATA
|
||||
add wave -hex /testbench/HRDATA
|
||||
add wave -hex /testbench/readAdrExpected
|
||||
add wave -divider W
|
||||
add wave -hex /testbench/PCW
|
||||
add wave -hex /testbench/PCtextW
|
||||
add wave -hex /testbench/dut/hart/ieu/c/InstrValidW
|
||||
add wave /testbench/dut/hart/ieu/dp/RegWriteW
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/ResultW
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/RdW
|
||||
|
||||
add wave -divider RegFile
|
||||
add wave -hex /testbench/regExpected
|
||||
add wave -hex /testbench/regNumExpected
|
||||
add wave -hex /testbench/HWRITE
|
||||
add wave -hex /testbench/dut/hart/MemRWM[1]
|
||||
add wave -hex /testbench/HWDATA
|
||||
add wave -hex /testbench/HRDATA
|
||||
add wave -hex /testbench/HADDR
|
||||
add wave -hex /testbench/readAdrExpected
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[1]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[2]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[3]
|
||||
@ -84,36 +92,10 @@ add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[28]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[29]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[30]
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[31]
|
||||
add wave /testbench/InstrFName
|
||||
add wave -hex /testbench/dut/hart/ifu/PCD
|
||||
#add wave -hex /testbench/dut/hart/ifu/InstrD
|
||||
add wave /testbench/InstrDName
|
||||
#add wave -divider
|
||||
add wave -hex /testbench/dut/hart/ifu/PCE
|
||||
##add wave -hex /testbench/dut/hart/ifu/InstrE
|
||||
add wave /testbench/InstrEName
|
||||
#add wave -hex /testbench/dut/hart/ieu/dp/SrcAE
|
||||
#add wave -hex /testbench/dut/hart/ieu/dp/SrcBE
|
||||
add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE
|
||||
#add wave /testbench/dut/hart/ieu/dp/PCSrcE
|
||||
#add wave -divider
|
||||
add wave -hex /testbench/dut/hart/ifu/PCM
|
||||
##add wave -hex /testbench/dut/hart/ifu/InstrM
|
||||
add wave /testbench/InstrMName
|
||||
#add wave /testbench/dut/hart/dmem/dtim/memwrite
|
||||
#add wave -hex /testbench/dut/hart/dmem/AdrM
|
||||
#add wave -hex /testbench/dut/hart/dmem/WriteDataM
|
||||
#add wave -divider
|
||||
add wave -hex /testbench/PCW
|
||||
##add wave -hex /testbench/dut/hart/ifu/InstrW
|
||||
add wave /testbench/InstrWName
|
||||
#add wave /testbench/dut/hart/ieu/dp/RegWriteW
|
||||
#add wave -hex /testbench/dut/hart/ieu/dp/ResultW
|
||||
#add wave -hex /testbench/dut/hart/ieu/dp/RdW
|
||||
#add wave -divider
|
||||
##add ww
|
||||
|
||||
add wave -divider
|
||||
add wave -hex -r /testbench/*
|
||||
#
|
||||
|
||||
# appearance
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {100 ps}
|
||||
@ -39,6 +39,7 @@ module csr #(parameter
|
||||
input logic InterruptM,
|
||||
input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, uretM,
|
||||
input logic TimerIntM, ExtIntM, SwIntM,
|
||||
input logic [63:0] MTIME, MTIMECMP,
|
||||
input logic InstrValidW, FloatRegWriteW, LoadStallD,
|
||||
input logic BPPredDirWrongM,
|
||||
input logic BTBPredPCWrongM,
|
||||
|
||||
@ -27,11 +27,11 @@
|
||||
///////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
// Ben 06/17/21: I brought in MTIME, MTIMECMP from CLINT. *** this probably isn't perfect though because it doesn't yet provide the ability to change these through CSR writes; overall this whole thing might need some rethinking
|
||||
module csrc #(parameter
|
||||
MCYCLE = 12'hB00,
|
||||
// MTIME = 12'hB01, // address not specified in privileged spec. Consider moving to CLINT to match SiFive
|
||||
// MTIMECMP = 12'hB21, // not specified in privileged spec. Move to CLINT
|
||||
MTIMEadr = 12'hB01, // address not specified in privileged spec. Consider moving to CLINT to match SiFive
|
||||
MTIMECMPadr = 12'hB21, // not specified in privileged spec. Move to CLINT
|
||||
MINSTRET = 12'hB02,
|
||||
MHPMCOUNTERBASE = 12'hB00,
|
||||
//MHPMCOUNTER3 = 12'hB03,
|
||||
@ -39,8 +39,8 @@ module csrc #(parameter
|
||||
// ... more counters
|
||||
//MHPMCOUNTER31 = 12'hB1F,
|
||||
MCYCLEH = 12'hB80,
|
||||
// MTIMEH = 12'hB81, // address not specified in privileged spec. Consider moving to CLINT to match SiFive
|
||||
// MTIMECMPH = 12'hBA1, // not specified in privileged spec. Move to CLINT
|
||||
MTIMEHadr = 12'hB81, // address not specified in privileged spec. Consider moving to CLINT to match SiFive
|
||||
MTIMECMPHadr = 12'hBA1, // not specified in privileged spec. Move to CLINT
|
||||
MINSTRETH = 12'hB82,
|
||||
MHPMCOUNTERHBASE = 12'hB80,
|
||||
//MHPMCOUNTER3H = 12'hB83,
|
||||
@ -54,7 +54,7 @@ module csrc #(parameter
|
||||
// ... more counters
|
||||
//MHPMEVENT31 = 12'h33F,
|
||||
CYCLE = 12'hC00,
|
||||
// TIME = 12'hC01, // not specified
|
||||
TIME = 12'hC01,
|
||||
INSTRET = 12'hC02,
|
||||
HPMCOUNTERBASE = 12'hC00,
|
||||
//HPMCOUNTER3 = 12'hC03,
|
||||
@ -62,7 +62,7 @@ module csrc #(parameter
|
||||
// ...more counters
|
||||
//HPMCOUNTER31 = 12'hC1F,
|
||||
CYCLEH = 12'hC80,
|
||||
// TIMEH = 12'hC81, // not specified
|
||||
TIMEH = 12'hC81, // not specified
|
||||
INSTRETH = 12'hC82,
|
||||
HPMCOUNTERHBASE = 12'hC80
|
||||
//HPMCOUNTER3H = 12'hC83,
|
||||
@ -71,17 +71,18 @@ module csrc #(parameter
|
||||
//HPMCOUNTER31H = 12'hC9F
|
||||
) (
|
||||
input logic clk, reset,
|
||||
input logic StallD, StallE, StallM, StallW,
|
||||
input logic StallD, StallE, StallM, StallW,
|
||||
input logic InstrValidW, LoadStallD, CSRMWriteM,
|
||||
input logic BPPredDirWrongM,
|
||||
input logic BTBPredPCWrongM,
|
||||
input logic RASPredPCWrongM,
|
||||
input logic BPPredClassNonCFIWrongM,
|
||||
input logic [4:0] InstrClassM,
|
||||
input logic BPPredDirWrongM,
|
||||
input logic BTBPredPCWrongM,
|
||||
input logic RASPredPCWrongM,
|
||||
input logic BPPredClassNonCFIWrongM,
|
||||
input logic [4:0] InstrClassM,
|
||||
input logic [11:0] CSRAdrM,
|
||||
input logic [1:0] PrivilegeModeW,
|
||||
input logic [`XLEN-1:0] CSRWriteValM,
|
||||
input logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW,
|
||||
input logic [63:0] MTIME, MTIMECMP,
|
||||
output logic [`XLEN-1:0] CSRCReadValM,
|
||||
output logic IllegalCSRCAccessM
|
||||
);
|
||||
@ -112,12 +113,12 @@ module csrc #(parameter
|
||||
|
||||
// Counter adders with inhibits for power savings
|
||||
assign CYCLEPlusM = CYCLE_REGW + {63'b0, ~MCOUNTINHIBIT_REGW[0]};
|
||||
// assign TIMEPlusM = TIME_REGW + 1; // can't be inhibited
|
||||
//assign TIMEPlusM = TIME_REGW + 1; // can't be inhibited
|
||||
assign INSTRETPlusM = INSTRET_REGW + {63'b0, InstrValidW & ~MCOUNTINHIBIT_REGW[2]};
|
||||
//assign HPMCOUNTER3PlusM = HPMCOUNTER3_REGW + {63'b0, LoadStallD & ~MCOUNTINHIBIT_REGW[3]}; // count load stalls
|
||||
///assign HPMCOUNTER4PlusM = HPMCOUNTER4_REGW + {63'b0, 1'b0 & ~MCOUNTINHIBIT_REGW[4]}; // change to count signals
|
||||
//assign HPMCOUNTER4PlusM = HPMCOUNTER4_REGW + {63'b0, 1'b0 & ~MCOUNTINHIBIT_REGW[4]}; // change to count signals
|
||||
assign NextCYCLEM = WriteCYCLEM ? CSRWriteValM : CYCLEPlusM[`XLEN-1:0];
|
||||
// assign NextTIMEM = WriteTIMEM ? CSRWriteValM : TIMEPlusM[`XLEN-1:0];
|
||||
//assign NextTIMEM = WriteTIMEM ? CSRWriteValM : TIMEPlusM[`XLEN-1:0];
|
||||
assign NextINSTRETM = WriteINSTRETM ? CSRWriteValM : INSTRETPlusM[`XLEN-1:0];
|
||||
//assign NextHPMCOUNTER3M = WriteHPMCOUNTER3M ? CSRWriteValM : HPMCOUNTER3PlusM[`XLEN-1:0];
|
||||
//assign NextHPMCOUNTER4M = WriteHPMCOUNTER4M ? CSRWriteValM : HPMCOUNTER4PlusM[`XLEN-1:0];
|
||||
@ -211,7 +212,7 @@ module csrc #(parameter
|
||||
//flopr #(32) HPMCOUNTER4Hreg(clk, reset, NextHPMCOUNTER4HM, HPMCOUNTER4_REGW[63:32]);
|
||||
end
|
||||
|
||||
// eventually move TIME and TIMECMP to the CLINT
|
||||
// eventually move TIME and TIMECMP to the CLINT -- Ben 06/17/21: sure let's give that a shot!
|
||||
// run TIME off asynchronous reference clock
|
||||
// synchronize write enable to TIME
|
||||
// four phase handshake to synchronize reads from TIME
|
||||
@ -229,13 +230,13 @@ module csrc #(parameter
|
||||
if (CSRAdrM >= MHPMCOUNTERBASE+3 && CSRAdrM < MHPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CSRAdrM-MHPMCOUNTERBASE];
|
||||
else if (CSRAdrM >= HPMCOUNTERBASE+3 && CSRAdrM < HPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CSRAdrM-HPMCOUNTERBASE];
|
||||
else case (CSRAdrM)
|
||||
// MTIME: CSRCReadValM = TIME_REGW;
|
||||
// MTIMECMP: CSRCReadValM = TIMECMP_REGW;
|
||||
MTIMEadr: CSRCReadValM = MTIME;
|
||||
MTIMECMPadr: CSRCReadValM = MTIMECMP;
|
||||
MCYCLE: CSRCReadValM = CYCLE_REGW;
|
||||
MINSTRET: CSRCReadValM = INSTRET_REGW;
|
||||
//MHPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW;
|
||||
//MHPMCOUNTER4: CSRCReadValM = HPMCOUNTER4_REGW;
|
||||
// TIME: CSRCReadValM = TIME_REGW;
|
||||
TIME: CSRCReadValM = MTIME;
|
||||
CYCLE: CSRCReadValM = CYCLE_REGW;
|
||||
INSTRET: CSRCReadValM = INSTRET_REGW;
|
||||
//HPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW;
|
||||
@ -258,24 +259,24 @@ module csrc #(parameter
|
||||
else if (CSRAdrM >= MHPMCOUNTERHBASE+3 && CSRAdrM < MHPMCOUNTERHBASE+`COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CSRAdrM-MHPMCOUNTERHBASE];
|
||||
else if (CSRAdrM >= HPMCOUNTERHBASE+3 && CSRAdrM < HPMCOUNTERHBASE+`COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CSRAdrM-HPMCOUNTERHBASE];
|
||||
else case (CSRAdrM)
|
||||
// MTIME: CSRCReadValM = TIME_REGW[31:0];
|
||||
// MTIMECMP: CSRCReadValM = TIMECMP_REGW[31:0];
|
||||
MTIMEadr: CSRCReadValM = MTIME[31:0];
|
||||
MTIMECMPadr: CSRCReadValM = MTIMECMP[31:0];
|
||||
MCYCLE: CSRCReadValM = CYCLE_REGW[31:0];
|
||||
MINSTRET: CSRCReadValM = INSTRET_REGW[31:0];
|
||||
//MHPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW[31:0];
|
||||
//MHPMCOUNTER4: CSRCReadValM = HPMCOUNTER4_REGW[31:0];
|
||||
// TIME: CSRCReadValM = TIME_REGW[31:0];
|
||||
TIME: CSRCReadValM = MTIME[31:0];
|
||||
CYCLE: CSRCReadValM = CYCLE_REGW[31:0];
|
||||
INSTRET: CSRCReadValM = INSTRET_REGW[31:0];
|
||||
//HPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW[31:0];
|
||||
//HPMCOUNTER4: CSRCReadValM = HPMCOUNTER4_REGW[31:0];
|
||||
// MTIMEH: CSRCReadValM = TIME_REGW[63:32];
|
||||
// MTIMECMPH: CSRCReadValM = TIMECMP_REGW[63:32];
|
||||
MTIMEHadr: CSRCReadValM = MTIME[63:32];
|
||||
MTIMECMPHadr: CSRCReadValM = MTIMECMP[63:32];
|
||||
MCYCLEH: CSRCReadValM = CYCLE_REGW[63:32];
|
||||
MINSTRETH: CSRCReadValM = INSTRET_REGW[63:32];
|
||||
//MHPMCOUNTER3H: CSRCReadValM = HPMCOUNTER3_REGW[63:32];
|
||||
//MHPMCOUNTER4H: CSRCReadValM = HPMCOUNTER4_REGW[63:32];
|
||||
// TIMEH: CSRCReadValM = TIME_REGW[63:32];
|
||||
TIMEH: CSRCReadValM = MTIME[63:32];
|
||||
CYCLEH: CSRCReadValM = CYCLE_REGW[63:32];
|
||||
INSTRETH: CSRCReadValM = INSTRET_REGW[63:32];
|
||||
//HPMCOUNTER3H: CSRCReadValM = HPMCOUNTER3_REGW[63:32];
|
||||
|
||||
@ -172,7 +172,7 @@ module csrm #(parameter
|
||||
// There are PMP_ENTRIES = 0, 16, or 64 PMPADDR registers, each of which has its own flop
|
||||
generate
|
||||
genvar i;
|
||||
for (i = 0; i < `PMP_ENTRIES-1; i++) begin: pmp_flop
|
||||
for (i = 0; i < `PMP_ENTRIES; i++) begin: pmp_flop
|
||||
flopenr #(`XLEN) PMPADDRreg(clk, reset, WritePMPADDRM[i], CSRWriteValM, PMPADDR_ARRAY_REGW[i]);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
@ -52,6 +52,7 @@ module privileged (
|
||||
input logic LoadMisalignedFaultM,
|
||||
input logic StoreMisalignedFaultM,
|
||||
input logic TimerIntM, ExtIntM, SwIntM,
|
||||
input logic [63:0] MTIME, MTIMECMP,
|
||||
input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM,
|
||||
input logic [4:0] SetFflagsM,
|
||||
|
||||
|
||||
@ -36,9 +36,9 @@ module clint (
|
||||
input logic [1:0] HTRANS,
|
||||
output logic [`XLEN-1:0] HREADCLINT,
|
||||
output logic HRESPCLINT, HREADYCLINT,
|
||||
output logic [63:0] MTIME, MTIMECMP,
|
||||
output logic TimerIntM, SwIntM);
|
||||
|
||||
logic [63:0] MTIMECMP, MTIME;
|
||||
logic MSIP;
|
||||
|
||||
logic [15:0] entry, entryd;
|
||||
|
||||
@ -57,7 +57,8 @@ module uncore (
|
||||
input logic [31:0] GPIOPinsIn,
|
||||
output logic [31:0] GPIOPinsOut, GPIOPinsEn,
|
||||
input logic UARTSin,
|
||||
output logic UARTSout
|
||||
output logic UARTSout,
|
||||
output logic [63:0] MTIME, MTIMECMP
|
||||
);
|
||||
|
||||
logic [`XLEN-1:0] HWDATA;
|
||||
|
||||
@ -34,6 +34,7 @@ module wallypipelinedhart (
|
||||
input logic TimerIntM, ExtIntM, SwIntM,
|
||||
input logic InstrAccessFaultF,
|
||||
input logic DataAccessFaultM,
|
||||
input logic [63:0] MTIME, MTIMECMP,
|
||||
// Bus Interface
|
||||
input logic [15:0] rd2, // bogus, delete when real multicycle fetch works
|
||||
input logic [`AHBW-1:0] HRDATA,
|
||||
|
||||
@ -63,6 +63,7 @@ module wallypipelinedsoc (
|
||||
logic [5:0] HSELRegions;
|
||||
logic InstrAccessFaultF, DataAccessFaultM;
|
||||
logic TimerIntM, SwIntM; // from CLINT
|
||||
logic [63:0] MTIME, MTIMECMP; // from CLINT to CSRs
|
||||
logic ExtIntM; // from PLIC
|
||||
logic [2:0] HADDRD;
|
||||
logic [3:0] HSIZED;
|
||||
|
||||
@ -162,7 +162,7 @@ module testbench();
|
||||
// read CSR trace file
|
||||
integer data_file_csr, scan_file_csr;
|
||||
initial begin
|
||||
data_file_csr = $fopen({`LINUX_TEST_VECTORS,"parsedCSRs2.txt"}, "r");
|
||||
data_file_csr = $fopen({`LINUX_TEST_VECTORS,"parsedCSRs.txt"}, "r");
|
||||
if (data_file_csr == 0) begin
|
||||
$display("file couldn't be opened");
|
||||
$stop;
|
||||
@ -473,7 +473,21 @@ module testbench();
|
||||
end
|
||||
end
|
||||
|
||||
string PCtext, PCtext2;
|
||||
string PCtextD,PCtextE,PCtextM,PCtext2;
|
||||
always_ff @(posedge clk, posedge reset)
|
||||
if (reset) begin
|
||||
PCtextE <= #1 "(reset)";
|
||||
PCtextM <= #1 "(reset)";
|
||||
end else begin
|
||||
if (~dut.hart.StallE)
|
||||
if (dut.hart.FlushE) PCtextE <= #1 "(flushed)";
|
||||
else PCtextE <= #1 PCtextD;
|
||||
if (~dut.hart.StallM)
|
||||
if (dut.hart.FlushM) PCtextM <= #1 "(flushed)";
|
||||
else PCtextM <= #1 PCtextE;
|
||||
end
|
||||
|
||||
|
||||
initial begin
|
||||
instrs = 0;
|
||||
end
|
||||
@ -495,7 +509,7 @@ module testbench();
|
||||
(dut.hart.ifu.PCD == 32'h80001dc6) || // as well as stores to PLIC
|
||||
(dut.hart.ifu.PCD == 32'h80001de0) ||
|
||||
(dut.hart.ifu.PCD == 32'h80001de2)) begin
|
||||
$display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtext, dut.hart.ifu.PCD, instrs, $time);
|
||||
$display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtextD, dut.hart.ifu.PCD, instrs, $time);
|
||||
force CheckInstrD = 32'b0010011;
|
||||
force dut.hart.ifu.InstrRawD = 32'b0010011;
|
||||
while (clk != 0) #1;
|
||||
@ -515,10 +529,10 @@ module testbench();
|
||||
$display("no more PC data to read");
|
||||
`ERROR
|
||||
end
|
||||
scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext);
|
||||
scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtextD);
|
||||
PCtext2 = "";
|
||||
while (PCtext2 != "***") begin
|
||||
PCtext = {PCtext, " ", PCtext2};
|
||||
PCtextD = {PCtextD, " ", PCtext2};
|
||||
scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext2);
|
||||
end
|
||||
scan_file_PC = $fscanf(data_file_PC, "%x\n", CheckInstrD);
|
||||
@ -527,7 +541,7 @@ module testbench();
|
||||
(dut.hart.ifu.PCD == 32'h80001dc6) || // as well as stores to PLIC
|
||||
(dut.hart.ifu.PCD == 32'h80001de0) ||
|
||||
(dut.hart.ifu.PCD == 32'h80001de2)) begin
|
||||
$display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtext, dut.hart.ifu.PCD, instrs, $time);
|
||||
$display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtextD, dut.hart.ifu.PCD, instrs, $time);
|
||||
force CheckInstrD = 32'b0010011;
|
||||
force dut.hart.ifu.InstrRawD = 32'b0010011;
|
||||
while (clk != 0) #1;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user