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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

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This commit is contained in:
Ross Thompson 2022-12-01 11:47:54 -06:00
commit da92cdccd0
2 changed files with 7 additions and 8 deletions
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8
pipelined/src/hazard/hazard.sv
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@ -65,15 +65,15 @@ module hazard(
assign StallFCause = CSRWriteFencePendingDEM & ~(TrapM | RetM | BPPredWrongE);
// stall in decode if instruction is a load/mul/csr dependent on previous
assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FPUStallD | FStallD) & ~(TrapM | RetM | BPPredWrongE);
// assign StallECause = (DivBusyE | FDivBusyE) & ~(TrapM); // *** can we move to decode stage (KP?)
assign StallECause = (DivBusyE) & ~(TrapM); // *** can we move to decode stage (KP?)
// WFI terminates if any enabled interrupt is pending, even if global interrupts are disabled. It could also terminate with TW trap
// assign StallMCause = (wfiM & (~TrapM & ~IntPendingM)); // | FDivBusyE;
assign StallMCause = ((wfiM) & (~TrapM & ~IntPendingM)); //*** Ross: should FDivBusyE trigger StallECause rather than StallMCause similar to DivBusyE?
// *** ross: my changes to cache and lsu need to disable ifu/lsu stalls on a Trap.
assign StallMCause = ((wfiM) & (~TrapM & ~IntPendingM));
assign StallWCause = ((IFUStallF | LSUStallM) & ~TrapM) | (FDivBusyE & ~TrapM & ~IntPendingM);
// head version
// assign StallWCause = LSUStallM | IFUStallF | (FDivBusyE & ~TrapM & ~IntPendingM); // *** FDivBusyE should look like DivBusyE
// assign StallMCause = (wfiM & (~TrapM & ~IntPendingM)); // | FDivBusyE;
// assign StallECause = (DivBusyE | FDivBusyE) & ~(TrapM); // *** can we move to decode stage (KP?)
// *** ross: my changes to cache and lsu need to disable ifu/lsu stalls on a Trap.
assign #1 StallF = StallFCause | StallD;

7
pipelined/src/muldiv/intdivrestoring.sv
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@ -50,7 +50,7 @@ module intdivrestoring (
logic [`XLEN-1:0] W[`DIV_BITSPERCYCLE:0];
logic [`XLEN-1:0] XQ[`DIV_BITSPERCYCLE:0];
logic [`XLEN-1:0] DinE, XinE, DnE, DAbsBE, DAbsBM, XnE, XInitE, WnM, XQnM;
logic [`XLEN-1:0] DinE, XinE, DnE, DAbsBE, DAbsB, XnE, XInitE, WnM, XQnM;
localparam STEPBITS = $clog2(`XLEN/`DIV_BITSPERCYCLE);
logic [STEPBITS:0] step;
logic Div0E, Div0M;
@ -86,7 +86,6 @@ module intdivrestoring (
neg #(`XLEN) negx(XinE, XnE);
mux3 #(`XLEN) xabsmux(XinE, XnE, ForwardedSrcAE, {Div0E, SignXE}, XInitE); // take absolute value for signed operations, or keep original value for divide by 0
//////////////////////////////
// Division Iterations (effectively stalled execute stage, no suffix)
//////////////////////////////
@ -98,17 +97,17 @@ module intdivrestoring (
// registers before division steps
flopen #(`XLEN) wreg(clk, DivBusyE, WNext, W[0]);
flopen #(`XLEN) xreg(clk, DivBusyE, XQNext, XQ[0]);
flopen #(`XLEN) dabsreg(clk, DivStartE, DAbsBE, DAbsB);
// one copy of divstep for each bit produced per cycle
genvar i;
for (i=0; i<`DIV_BITSPERCYCLE; i = i+1)
intdivrestoringstep divstep(W[i], XQ[i], DAbsBM, W[i+1], XQ[i+1]);
intdivrestoringstep divstep(W[i], XQ[i], DAbsB, W[i+1], XQ[i+1]);
//////////////////////////////
// Memory Stage: output sign correction and special cases
//////////////////////////////
flopen #(`XLEN) dabsreg(clk, DivStartE, DAbsBE, DAbsBM);
flopen #(3) Div0eMReg(clk, DivStartE, {Div0E, NegQE, SignXE}, {Div0M, NegQM, NegWM});
// On final setp of signed operations, negate outputs as needed to get correct sign