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Removed reset on dirty cache bits.

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This commit is contained in:
Ross Thompson 2022-11-30 11:04:37 -06:00
parent 5e5cca6ae1
commit da7b13ba0a
1 changed files with 4 additions and 4 deletions
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8
pipelined/src/cache/cacheway.sv vendored
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@ -130,9 +130,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
if (reset) ValidBits <= #1 '0; if (reset) ValidBits <= #1 '0;
if(ce) begin if(ce) begin
ValidWay <= #1 ValidBits[CAdr]; ValidWay <= #1 ValidBits[CAdr];
if(InvalidateCache & ~FlushStage) ValidBits <= #1 '0; if(InvalidateCache & ~FlushStage) ValidBits <= #1 '0;
else if (SetValidEN) ValidBits[CAdr] <= #1 1'b1; else if (SetValidEN | (ClearValidWay & ~FlushStage)) ValidBits[CAdr] <= #1 SetValidWay;
else if (ClearValidWay & ~FlushStage) ValidBits[CAdr] <= #1 1'b0;
end end
end end
@ -143,7 +142,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
// Dirty bits // Dirty bits
if (DIRTY_BITS) begin:dirty if (DIRTY_BITS) begin:dirty
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if (reset) DirtyBits <= #1 {NUMLINES{1'b0}}; // reset is optional. Consider merging with TAG array in the future. // reset is optional. Consider merging with TAG array in the future.
//if (reset) DirtyBits <= #1 {NUMLINES{1'b0}};
if(ce) begin if(ce) begin
Dirty <= #1 DirtyBits[CAdr]; Dirty <= #1 DirtyBits[CAdr];
if((SetDirtyWay | ClearDirtyWay) & ~FlushStage) DirtyBits[CAdr] <= #1 SetDirtyWay; if((SetDirtyWay | ClearDirtyWay) & ~FlushStage) DirtyBits[CAdr] <= #1 SetDirtyWay;