Light cleanup of signals, style. Changed several signals to account for new Phys Addr sizes as opposed to HADDR.

wally-pipelined/config/rv32ic/wally-config.vh

@@ -61,26 +61,27 @@
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
 
+// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
 `define BOOTTIM_SUPPORTED 1'b1
-`define BOOTTIM_BASE   32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
+`define BOOTTIM_BASE   34'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
-`define BOOTTIM_RANGE  32'h00003FFF
+`define BOOTTIM_RANGE  34'h00003FFF
-//`define BOOTTIM_BASE   32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
+//`define BOOTTIM_BASE   34'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
-//`define BOOTTIM_RANGE  32'h00000FFF
+//`define BOOTTIM_RANGE  34'h00000FFF
 `define TIM_SUPPORTED 1'b1
-`define TIM_BASE       32'h80000000
+`define TIM_BASE       34'h80000000
-`define TIM_RANGE      32'h07FFFFFF
+`define TIM_RANGE      34'h07FFFFFF
 `define CLINT_SUPPORTED 1'b1
-`define CLINT_BASE  32'h02000000
+`define CLINT_BASE  34'h02000000
-`define CLINT_RANGE 32'h0000FFFF
+`define CLINT_RANGE 34'h0000FFFF
 `define GPIO_SUPPORTED 1'b1
-`define GPIO_BASE   32'h10012000
+`define GPIO_BASE   34'h10012000
-`define GPIO_RANGE  32'h000000FF
+`define GPIO_RANGE  34'h000000FF
 `define UART_SUPPORTED 1'b1
-`define UART_BASE   32'h10000000
+`define UART_BASE   34'h10000000
-`define UART_RANGE  32'h00000007
+`define UART_RANGE  34'h00000007
 `define PLIC_SUPPORTED 1'b1
-`define PLIC_BASE   32'h0C000000
+`define PLIC_BASE   34'h0C000000
-`define PLIC_RANGE  32'h03FFFFFF
+`define PLIC_RANGE  34'h03FFFFFF
 
 // Bus Interface width
 `define AHBW 32

wally-pipelined/config/rv64ic/wally-config.vh

@@ -65,26 +65,27 @@
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
 
+// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
 `define BOOTTIM_SUPPORTED 1'b1
-`define BOOTTIM_BASE   32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
+`define BOOTTIM_RANGE  56'h00003FFF
-`define BOOTTIM_RANGE  32'h00003FFF
+`define BOOTTIM_BASE   56'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
-//`define BOOTTIM_BASE   32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
+//`define BOOTTIM_BASE   56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
-//`define BOOTTIM_RANGE  32'h00000FFF
+//`define BOOTTIM_RANGE  56'h00000FFF
 `define TIM_SUPPORTED 1'b1
-`define TIM_BASE       32'h80000000
+`define TIM_BASE       56'h80000000
-`define TIM_RANGE      32'h07FFFFFF
+`define TIM_RANGE      56'h07FFFFFF
 `define CLINT_SUPPORTED 1'b1
-`define CLINT_BASE  32'h02000000
+`define CLINT_BASE  56'h02000000
-`define CLINT_RANGE 32'h0000FFFF
+`define CLINT_RANGE 56'h0000FFFF
 `define GPIO_SUPPORTED 1'b1
-`define GPIO_BASE   32'h10012000
+`define GPIO_BASE   56'h10012000
-`define GPIO_RANGE  32'h000000FF
+`define GPIO_RANGE  56'h000000FF
 `define UART_SUPPORTED 1'b1
-`define UART_BASE   32'h10000000
+`define UART_BASE   56'h10000000
-`define UART_RANGE  32'h00000007
+`define UART_RANGE  56'h00000007
 `define PLIC_SUPPORTED 1'b1
-`define PLIC_BASE   32'h0C000000
+`define PLIC_BASE   56'h0C000000
-`define PLIC_RANGE  32'h03FFFFFF
+`define PLIC_RANGE  56'h03FFFFFF
 
 // Test modes
 

wally-pipelined/src/lsu/lsuArb.sv

@@ -93,17 +93,17 @@ module lsuArb
   always_comb begin
     case(CurrState)
       StateReady: 
-	if (HPTWTranslate & DataStall) NextState = StatePTWPending;
+	      if      (HPTWTranslate & DataStall)  NextState = StatePTWPending;
         else if (HPTWTranslate & ~DataStall) NextState = StatePTWActive;
-	else NextState = StateReady;
+	      else                                 NextState = StateReady;
       StatePTWPending:
-	if (~DataStall) NextState = StatePTWActive;
+	      if (~DataStall)                      NextState = StatePTWActive;
-	else NextState = StatePTWPending;
+	      else                                 NextState = StatePTWPending;
       StatePTWActive:
-	if (~DataStall) NextState = StateReady;
+	      if (~DataStall)                      NextState = StateReady;
-	else NextState = StatePTWActive;
+	      else                                 NextState = StatePTWActive;
-      default: NextState = StateReady;
+      default:                               NextState = StateReady;
-    endcase // case (CurrState)
+    endcase
   end
 
 

wally-pipelined/src/uncore/dtim.sv

@@ -37,8 +37,8 @@ module dtim #(parameter BASE=0, RANGE = 65535) (
   output logic             HRESPTim, HREADYTim
 );
 
-  localparam integer 	   MemStartAddr = BASE>>(1+`XLEN/32);
+  localparam MemStartAddr = BASE>>(1+`XLEN/32);
-  localparam integer 	   MemEndAddr = (RANGE+BASE)>>1+(`XLEN/32);
+  localparam MemEndAddr = (RANGE+BASE)>>1+(`XLEN/32);
   
   logic [`XLEN-1:0] RAM[BASE>>(1+`XLEN/32):(RANGE+BASE)>>1+(`XLEN/32)];
   logic [31:0] HWADDR, A;

wally-pipelined/src/uncore/uncore.sv

@@ -74,7 +74,7 @@ module uncore (
 
   // Determine which region of physical memory (if any) is being accessed
   // Use a trimmed down portion of the PMA checker - only the address decoders
-  adrdecs adrdecs(HADDR, 1'b1, 1'b1, 1'b1, HSIZE, HSELRegions);
+  adrdecs adrdecs({{(`PA_BITS-32){1'b0}}, HADDR}, 1'b1, 1'b1, 1'b1, HSIZE[1:0], HSELRegions);
 
   // unswizzle HSEL signals
   assign {HSELBootTim, HSELTim, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC} = HSELRegions;

wally-pipelined/src/wally/wallypipelinedhart.sv

@@ -120,10 +120,10 @@ module wallypipelinedhart
   logic 		    PMPInstrAccessFaultF, PMPLoadAccessFaultM, PMPStoreAccessFaultM;
   logic 		    PMAInstrAccessFaultF, PMALoadAccessFaultM, PMAStoreAccessFaultM;
   logic 		    DSquashBusAccessM, ISquashBusAccessF;
-  logic [5:0] 		    DHSELRegionsM, IHSELRegionsF;
+//  logic [5:0] 		    DHSELRegionsM, IHSELRegionsF;
   var logic [`XLEN-1:0]     PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0];
   logic [63:0] 		    PMPCFG01_REGW, PMPCFG23_REGW; // signals being sent from privileged unit to pmp/pma in dmem and ifu.
-  assign            HSELRegions = ExecuteAccessF ? IHSELRegionsF : DHSELRegionsM; // *** this is a pure guess on how one of these should be selected. it passes tests, but is it the right way to do this?
+//  assign            HSELRegions = ExecuteAccessF ? IHSELRegionsF : DHSELRegionsM; // *** this is a pure guess on how one of these should be selected. it passes tests, but is it the right way to do this?
 
   // IMem stalls
   logic 		    ICacheStallF;