forked from Github_Repos/cvw
Regression test runs further. The LSU state machine which fakes the Dcache had a few bugs. MemAccessM needed to be squashed on bus faults.
This commit is contained in:
Ross Thompson
parent
d7e518991e
commit
d6c19e73f4
@ -30,8 +30,7 @@
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`define BUILDROOT 0
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`define BUILDROOT 0
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`define BUSYBEAR 1
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`define BUSYBEAR 1
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`define LINUX_FIX_READ {'h10000005}
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`define LINUX_FIX_READ {'h10000005}
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`define LINUX_TEST_VECTORS "../../../busybear_boot/"
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`define LINUX_TEST_VECTORS "/courses/e190ax/busybear_boot/"
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//`define LINUX_TEST_VECTORS "/courses/e190ax/busybear_boot/"
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// RV32 or RV64: XLEN = 32 or 64
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// RV32 or RV64: XLEN = 32 or 64
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`define XLEN 64
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`define XLEN 64
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@ -7,37 +7,37 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/Func
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/DataStall
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/DataStall
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM
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add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/hart/StallF
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/hart/StallD
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/hart/StallE
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/hart/StallM
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/hart/StallW
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add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
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add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
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@ -117,18 +117,18 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/result
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/flags
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add wave -noupdate -group alu -divider internals
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add wave -noupdate -expand -group alu -divider internals
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/overflow
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/carry
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/zero
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu
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add wave -noupdate -group dcache -expand -group {cpu request} /testbench/dut/hart/MemAdrM
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add wave -noupdate -group dcache -expand -group {cpu request} /testbench/dut/hart/MemAdrM
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add wave -noupdate -group dcache -expand -group {cpu request} /testbench/dut/hart/WriteDataM
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add wave -noupdate -group dcache -expand -group {cpu request} /testbench/dut/hart/WriteDataM
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add wave -noupdate -group dcache /testbench/dut/hart/MemPAdrM
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add wave -noupdate -group dcache /testbench/dut/hart/MemPAdrM
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@ -235,8 +235,52 @@ add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HADDRD
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HSIZED
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HSIZED
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HWRITED
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add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HWRITED
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/CurrState
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/CurrState
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add wave -noupdate -expand -group lsu /testbench/dut/hart/arbiter/MemAdrM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemPAdrM
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add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/DSquashBusAccessM
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HCLK
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HSELPLIC
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HADDR
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HWRITE
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HREADY
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HTRANS
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HWDATA
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/UARTIntr
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/GPIOIntr
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HREADPLIC
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HRESPPLIC
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HREADYPLIC
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/ExtIntM
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HCLK
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HSELGPIO
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HADDR
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HWDATA
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HWRITE
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADY
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HTRANS
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADGPIO
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HRESPGPIO
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADYGPIO
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsIn
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsOut
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsEn
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOIntr
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HCLK
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HSELCLINT
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HADDR
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HWRITE
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HWDATA
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADY
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HTRANS
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADCLINT
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HRESPCLINT
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADYCLINT
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM
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TreeUpdate [SetDefaultTree]
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 4} {32648010 ns} 0} {{Cursor 5} {4216 ns} 0}
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WaveRestoreCursors {{Cursor 4} {32648010 ns} 0} {{Cursor 5} {14425 ns} 0}
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quietly wave cursor active 2
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quietly wave cursor active 2
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configure wave -namecolwidth 250
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 189
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configure wave -valuecolwidth 189
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@ -252,4 +296,4 @@ configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timeline 0
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configure wave -timelineunits ns
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configure wave -timelineunits ns
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update
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update
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WaveRestoreZoom {4167 ns} {4406 ns}
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WaveRestoreZoom {0 ns} {2330991 ns}
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@ -156,7 +156,7 @@ module lsu (
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assign MemReadM = MemRWM[1] & ~NonBusTrapM & CurrState != STATE_STALLED;
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assign MemReadM = MemRWM[1] & ~NonBusTrapM & CurrState != STATE_STALLED;
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assign MemWriteM = MemRWM[0] & ~NonBusTrapM && ~SquashSCM & CurrState != STATE_STALLED;
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assign MemWriteM = MemRWM[0] & ~NonBusTrapM && ~SquashSCM & CurrState != STATE_STALLED;
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assign AtomicMaskedM = CurrState != STATE_STALLED ? AtomicM : 2'b00 ;
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assign AtomicMaskedM = CurrState != STATE_STALLED ? AtomicM : 2'b00 ;
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assign MemAccessM = |MemRWM;
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assign MemAccessM = MemReadM | MemWriteM;
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// Determine if M stage committed
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// Determine if M stage committed
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// Reset whenever unstalled. Set when access successfully occurs
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// Reset whenever unstalled. Set when access successfully occurs
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@ -195,7 +195,7 @@ module lsu (
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endgenerate
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endgenerate
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// Data stall
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// Data stall
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assign DataStall = (CurrState == STATE_FETCH) || (CurrState == STATE_FETCH_AMO);
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assign DataStall = (NextState == STATE_FETCH) || (NextState == STATE_FETCH_AMO);
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// Ross Thompson April 22, 2021
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// Ross Thompson April 22, 2021
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// for now we need to handle the issue where the data memory interface repeately
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// for now we need to handle the issue where the data memory interface repeately
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@ -209,7 +209,7 @@ module lsu (
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always_comb begin
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always_comb begin
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case (CurrState)
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case (CurrState)
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STATE_READY: if (MemRWM[1] & MemRWM[0]) NextState = STATE_FETCH_AMO; // *** should be some misalign check
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STATE_READY: if (|AtomicMaskedM) NextState = STATE_FETCH_AMO; // *** should be some misalign check
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else if (MemAccessM & ~DataMisalignedM) NextState = STATE_FETCH;
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else if (MemAccessM & ~DataMisalignedM) NextState = STATE_FETCH;
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else NextState = STATE_READY;
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else NextState = STATE_READY;
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STATE_FETCH_AMO: if (MemAckW) NextState = STATE_FETCH;
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STATE_FETCH_AMO: if (MemAckW) NextState = STATE_FETCH;
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Loading…
Reference in New Issue
Block a user