forked from Github_Repos/cvw
Write Hits and Write Misses without eviction are working correctly! The next
step is to add eviction of dirty lines.
This commit is contained in:
Ross Thompson
parent
b1ceeb40df
commit
d65c01bc29
3
wally-pipelined/src/cache/DCacheMem.sv
vendored
3
wally-pipelined/src/cache/DCacheMem.sv
vendored
@ -33,6 +33,7 @@ module DCacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26
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input logic [$clog2(NUMLINES)-1:0] WAdr, // write address for valid and dirty only
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input logic WriteEnable,
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input logic [BLOCKLEN/`XLEN-1:0] WriteWordEnable,
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input logic TagWriteEnable,
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input logic [BLOCKLEN-1:0] WriteData,
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input logic [TAGLEN-1:0] WriteTag,
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input logic SetValid,
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@ -69,7 +70,7 @@ module DCacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26
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.Addr(Adr),
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.ReadData(ReadTag),
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.WriteData(WriteTag),
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.WriteEnable(WriteEnable));
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.WriteEnable(TagWriteEnable));
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always_ff @(posedge clk, posedge reset) begin
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120
wally-pipelined/src/cache/dcache.sv
vendored
120
wally-pipelined/src/cache/dcache.sv
vendored
@ -59,7 +59,7 @@ module dcache
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);
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localparam integer BLOCKLEN = 256;
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localparam integer NUMLINES = 512;
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localparam integer NUMLINES = 64;
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localparam integer NUMWAYS = 4;
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localparam integer NUMREPL_BITS = 3;
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@ -127,7 +127,7 @@ module dcache
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// data path
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flopen #(`PA_BITS) MemPAdrWReg(.clk(clk),
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.en(~StallW),
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.en(1'b1),
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.d(MemPAdrM),
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.q(MemPAdrW));
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@ -137,15 +137,18 @@ module dcache
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.s(SelAdrM),
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.y(AdrMuxOut));
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assign SRAMAdr = AdrMuxOut;
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/* -----\/----- EXCLUDED -----\/-----
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mux2 #(INDEXLEN)
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SelAdrlMux2(.d0(AdrMuxOut),
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.d1(MemPAdrW[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
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.s(SRAMWordWriteEnableW),
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.y(SRAMAdr));
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-----/\----- EXCLUDED -----/\----- */
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oneHotDecoder #(LOGWPL)
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oneHotDecoder(.bin(MemPAdrW[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]),
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oneHotDecoder(.bin(MemPAdrM[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]),
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.decoded(MemPAdrDecodedW));
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@ -154,7 +157,7 @@ module dcache
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genvar way;
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generate
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for(way = 0; way < NUMWAYS; way = way + 1) begin
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for(way = 0; way < NUMWAYS; way = way + 1) begin :CacheWays
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DCacheMem #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN))
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MemWay(.clk(clk),
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.reset(reset),
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@ -162,12 +165,13 @@ module dcache
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.WAdr(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
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.WriteEnable(SRAMWayWriteEnable[way]),
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.WriteWordEnable(SRAMWordEnable),
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.TagWriteEnable(SRAMBlockWriteEnableM),
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.WriteData(SRAMWriteData),
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.WriteTag(MemPAdrW[`PA_BITS-1:OFFSETLEN+INDEXLEN]),
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.SetValid(SetValidW),
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.ClearValid(ClearValidW),
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.SetDirty(SetDirtyW),
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.ClearDirty(ClearDirtyW),
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.WriteTag(MemPAdrM[`PA_BITS-1:OFFSETLEN+INDEXLEN]),
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.SetValid(SetValidM),
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.ClearValid(ClearValidM),
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.SetDirty(SetDirtyM),
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.ClearDirty(ClearDirtyM),
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.ReadData(ReadDataBlockWayM[way]),
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.ReadTag(ReadTag[way]),
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.Valid(Valid[way]),
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@ -186,13 +190,13 @@ module dcache
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for(int index = 0; index < NUMLINES-1; index++)
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ReplacementBits[index] <= '0;
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end
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else if (SRAMWriteEnable) ReplacementBits[MemPAdrW[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= NewReplacement;
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else if (SRAMWriteEnable) ReplacementBits[MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= NewReplacement;
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end
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// *** TODO add replacement policy
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assign NewReplacement = '0;
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assign VictimWay = 4'b0001;
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mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWriteEnableW ? WayHit : '0),
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mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWriteEnableM ? WayHit : '0),
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.d1(SRAMBlockWriteEnableM ? VictimWay : '0),
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.s(SRAMBlockWriteEnableM),
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.y(SRAMWayWriteEnable));
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@ -308,39 +312,41 @@ module dcache
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logic CntReset;
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typedef enum {STATE_READY,
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STATE_READ_MISS_FETCH_WDV,
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STATE_READ_MISS_FETCH_DONE,
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STATE_READ_MISS_CHECK_EVICTED_DIRTY,
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STATE_READ_MISS_WRITE_BACK_EVICTED_BLOCK,
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STATE_READ_MISS_WRITE_CACHE_BLOCK,
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STATE_READ_MISS_READ_WORD,
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STATE_WRITE_MISS_FETCH_WDV,
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STATE_WRITE_MISS_FETCH_DONE,
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STATE_WRITE_MISS_CHECK_EVICTED_DIRTY,
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STATE_WRITE_MISS_WRITE_BACK_EVICTED_BLOCK,
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STATE_WRITE_MISS_WRITE_CACHE_BLOCK,
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STATE_WRITE_MISS_WRITE_WORD,
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STATE_AMO_MISS_FETCH_WDV,
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STATE_AMO_MISS_FETCH_DONE,
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STATE_AMO_MISS_CHECK_EVICTED_DIRTY,
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STATE_AMO_MISS_WRITE_BACK_EVICTED_BLOCK,
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STATE_AMO_MISS_WRITE_CACHE_BLOCK,
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STATE_AMO_MISS_READ_WORD,
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STATE_AMO_MISS_UPDATE_WORD,
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STATE_AMO_MISS_WRITE_WORD,
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STATE_AMO_UPDATE,
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STATE_AMO_WRITE,
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STATE_SRAM_BUSY,
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STATE_PTW_READY,
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STATE_PTW_MISS_FETCH_WDV,
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STATE_PTW_MISS_FETCH_DONE,
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STATE_PTW_MISS_CHECK_EVICTED_DIRTY,
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STATE_PTW_MISS_WRITE_BACK_EVICTED_BLOCK,
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STATE_PTW_MISS_WRITE_CACHE_BLOCK,
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STATE_PTW_MISS_READ_SRAM,
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STATE_UNCACHED_WDV,
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STATE_UNCACHED_DONE} statetype;
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typedef enum {STATE_READY,
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STATE_READ_MISS_FETCH_WDV,
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STATE_READ_MISS_FETCH_DONE,
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STATE_READ_MISS_CHECK_EVICTED_DIRTY,
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STATE_READ_MISS_WRITE_BACK_EVICTED_BLOCK,
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STATE_READ_MISS_WRITE_CACHE_BLOCK,
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STATE_READ_MISS_READ_WORD,
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STATE_WRITE_MISS_FETCH_WDV,
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STATE_WRITE_MISS_FETCH_DONE,
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STATE_WRITE_MISS_CHECK_EVICTED_DIRTY,
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STATE_WRITE_MISS_WRITE_BACK_EVICTED_BLOCK,
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STATE_WRITE_MISS_WRITE_CACHE_BLOCK,
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STATE_WRITE_MISS_READ_WORD,
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STATE_WRITE_MISS_WRITE_WORD,
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STATE_AMO_MISS_FETCH_WDV,
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STATE_AMO_MISS_FETCH_DONE,
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STATE_AMO_MISS_CHECK_EVICTED_DIRTY,
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STATE_AMO_MISS_WRITE_BACK_EVICTED_BLOCK,
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STATE_AMO_MISS_WRITE_CACHE_BLOCK,
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STATE_AMO_MISS_READ_WORD,
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STATE_AMO_MISS_UPDATE_WORD,
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STATE_AMO_MISS_WRITE_WORD,
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STATE_AMO_UPDATE,
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STATE_AMO_WRITE,
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STATE_SRAM_BUSY,
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STATE_PTW_READY,
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STATE_PTW_MISS_FETCH_WDV,
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STATE_PTW_MISS_FETCH_DONE,
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STATE_PTW_MISS_CHECK_EVICTED_DIRTY,
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STATE_PTW_MISS_WRITE_BACK_EVICTED_BLOCK,
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STATE_PTW_MISS_WRITE_CACHE_BLOCK,
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STATE_PTW_MISS_READ_SRAM,
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STATE_UNCACHED_WDV,
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STATE_UNCACHED_DONE,
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STATE_CPU_BUSY} statetype;
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statetype CurrState, NextState;
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@ -360,7 +366,7 @@ module dcache
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assign NextFetchCount = FetchCount + 1'b1;
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assign SRAMWriteEnable = SRAMBlockWriteEnableM | SRAMWordWriteEnableW;
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assign SRAMWriteEnable = SRAMBlockWriteEnableM | SRAMWordWriteEnableM;
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flopr #(1+4+2)
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SRAMWritePipeReg(.clk(clk),
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@ -419,10 +425,12 @@ module dcache
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end
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// write hit valid cached
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else if (MemRWM[0] & ~UncachedM & ~FaultM & CacheHit & ~DTLBMissM) begin
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NextState = STATE_READY;
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SelAdrM = 1'b1;
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DCacheStall = 1'b0;
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SRAMWordWriteEnableM = 1'b1;
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SetDirtyM = 1'b1;
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if(StallW) NextState = STATE_CPU_BUSY;
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else NextState = STATE_READY;
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end
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// read miss valid cached
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else if(MemRWM[1] & ~UncachedM & ~FaultM & ~CacheHit & ~DTLBMissM) begin
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@ -488,6 +496,7 @@ module dcache
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DCacheStall = 1'b1;
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PreCntEn = 1'b1;
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AHBRead = 1'b1;
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SelAdrM = 1'b1;
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if (FetchCountFlag & AHBAck) begin
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NextState = STATE_WRITE_MISS_FETCH_DONE;
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end else begin
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@ -497,6 +506,7 @@ module dcache
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STATE_WRITE_MISS_FETCH_DONE: begin
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DCacheStall = 1'b1;
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SelAdrM = 1'b1;
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if(VictimDirty) begin
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NextState = STATE_WRITE_MISS_CHECK_EVICTED_DIRTY;
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end else begin
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@ -507,16 +517,23 @@ module dcache
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STATE_WRITE_MISS_WRITE_CACHE_BLOCK: begin
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SRAMBlockWriteEnableM = 1'b1;
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DCacheStall = 1'b1;
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NextState = STATE_WRITE_MISS_WRITE_WORD;
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NextState = STATE_WRITE_MISS_READ_WORD;
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SelAdrM = 1'b1;
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SetValidM = 1'b1;
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end
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STATE_WRITE_MISS_READ_WORD: begin
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NextState = STATE_WRITE_MISS_WRITE_WORD;
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DCacheStall = 1'b1;
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SelAdrM = 1'b1;
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end
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STATE_WRITE_MISS_WRITE_WORD: begin
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SRAMWordWriteEnableM = 1'b1;
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DCacheStall = 1'b0;
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NextState = STATE_READY;
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SRAMWordWriteEnableM = 1'b1;
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SetDirtyM = 1'b1;
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NextState = STATE_READY;
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SelAdrM = 1'b1;
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end
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STATE_PTW_MISS_FETCH_WDV: begin
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@ -533,6 +550,11 @@ module dcache
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DCacheStall = 1'b0;
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NextState = STATE_READY;
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end
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STATE_CPU_BUSY : begin
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if(StallW) NextState = STATE_CPU_BUSY;
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else NextState = STATE_READY;
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end
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default: begin
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end
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endcase
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