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Similifed the no byte write enabled version of the sram model.

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Ross Thompson 2023-04-06 14:18:41 -05:00
parent fddbd79209
commit d121364997
1 changed files with 1 additions and 10 deletions
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src/generic/mem/ram1p1rwe.sv
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@ -90,16 +90,7 @@ module ram1p1rwe #(parameter DEPTH=64, WIDTH=44) (
// so we can never get we=1, ce=0 for I$. // so we can never get we=1, ce=0 for I$.
if (ce & we) if (ce & we)
// coverage on // coverage on
for(i = 0; i < WIDTH/8; i++) RAM[addr] <= #1 din;
RAM[addr][i*8 +: 8] <= #1 din[i*8 +: 8];
if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8
always @(posedge clk)
// coverage off
// (see the above explanation)
if (ce & we)
// coverage on
RAM[addr][WIDTH-1:WIDTH-WIDTH%8] <= #1 din[WIDTH-1:WIDTH-WIDTH%8];
end end
endmodule endmodule