forked from Github_Repos/cvw
Possible optimization of gshare.
I don't believe the Writeback stage ghr is needed.
This commit is contained in:
Ross Thompson
parent
ea7c447218
commit
cf608ee45f
@ -509,53 +509,6 @@ logic [3:0] dummy;
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$stop;
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end
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end
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/* -----\/----- EXCLUDED -----\/-----
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// rvvi tracer
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localparam int ILEN = `XLEN; // Instruction length in bits
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localparam int XLEN = `XLEN; // GPR length in bits
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localparam int FLEN = `FLEN; // FPR length in bits
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localparam int VLEN = 0; // Vector register size in bits
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localparam int NHART = 1; // Number of harts reported
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localparam int RETIRE = 1; // Number of instructions that can retire during valid event
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logic TraceClk; // Interface clock
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logic valid [(NHART-1):0][(RETIRE-1):0]; // Retired instruction
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logic [63:0] order [(NHART-1):0][(RETIRE-1):0]; // Unique instruction order count (no gaps or reuse)
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logic [(ILEN-1):0] insn [(NHART-1):0][(RETIRE-1):0]; // Instruction bit pattern
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logic trap [(NHART-1):0][(RETIRE-1):0]; // Trapped instruction
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logic halt [(NHART-1):0][(RETIRE-1):0]; // Halted instruction
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logic intr [(NHART-1):0][(RETIRE-1):0]; // (RVFI Legacy) Flag first instruction of trap handler
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logic [1:0] mode [(NHART-1):0][(RETIRE-1):0]; // Privilege mode of operation
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logic [1:0] ixl [(NHART-1):0][(RETIRE-1):0]; // XLEN mode 32/64 bit
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logic [(XLEN-1):0] pc_rdata [(NHART-1):0][(RETIRE-1):0]; // PC of insn
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logic [(XLEN-1):0] pc_wdata [(NHART-1):0][(RETIRE-1):0]; // PC of next instruction
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// X Registers
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logic [31:0][(XLEN-1):0] x_wdata [(NHART-1):0][(RETIRE-1):0]; // X data value
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logic [31:0] x_wb [(NHART-1):0][(RETIRE-1):0]; // X data writeback (change) flag
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// F Registers
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logic [31:0][(FLEN-1):0] f_wdata [(NHART-1):0][(RETIRE-1):0]; // F data value
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logic [31:0] f_wb [(NHART-1):0][(RETIRE-1):0]; // F data writeback (change) flag
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// V Registers
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logic [31:0][(VLEN-1):0] v_wdata [(NHART-1):0][(RETIRE-1):0]; // V data value
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logic [31:0] v_wb [(NHART-1):0][(RETIRE-1):0]; // V data writeback (change) flag
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// Control & State Registers
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logic [4095:0][(XLEN-1):0] csr [(NHART-1):0][(RETIRE-1):0]; // Full CSR Address range
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logic [4095:0] csr_wb [(NHART-1):0][(RETIRE-1):0]; // CSR writeback (change) flag
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logic lrsc_cancel[(NHART-1):0][(RETIRE-1):0]; // Implementation defined
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rvviTrace #(`XLEN, `XLEN, `FLEN, 0, 1, 1) rvviTrace(.clk(TraceClk), .valid, .order, .insn, .trap, .halt, .intr,
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.mode, .ixl, .pc_rdata, .pc_wdata, .x_wdata, .x_wb, .f_wdata, .f_wb, .v_wdata, .v_wb,
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.csr, .csr_wb, .lrsc_cancel);
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-----/\----- EXCLUDED -----/\----- */
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rvviTrace rvviTrace();
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endmodule
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@ -791,97 +744,3 @@ module rvviTrace();
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endmodule
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/* -----\/----- EXCLUDED -----\/-----
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module rvviTrace #(
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parameter int ILEN = `XLEN, // Instruction length in bits
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parameter int XLEN = `XLEN, // GPR length in bits
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parameter int FLEN = `FLEN, // FPR length in bits
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parameter int VLEN = 0, // Vector register size in bits
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parameter int NHART = 1, // Number of harts reported
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parameter int RETIRE = 1 // Number of instructions that can retire during valid event
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)(
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//
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// RISCV output signals
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//
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output logic clk, // Interface clock
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output logic valid [(NHART-1):0][(RETIRE-1):0], // Retired instruction
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output logic [63:0] order [(NHART-1):0][(RETIRE-1):0], // Unique instruction order count (no gaps or reuse)
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output logic [(ILEN-1):0] insn [(NHART-1):0][(RETIRE-1):0], // Instruction bit pattern
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output logic trap [(NHART-1):0][(RETIRE-1):0], // Trapped instruction
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output logic halt [(NHART-1):0][(RETIRE-1):0], // Halted instruction
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output logic intr [(NHART-1):0][(RETIRE-1):0], // (RVFI Legacy) Flag first instruction of trap handler
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output logic [1:0] mode [(NHART-1):0][(RETIRE-1):0], // Privilege mode of operation
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output logic [1:0] ixl [(NHART-1):0][(RETIRE-1):0], // XLEN mode 32/64 bit
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output logic [(XLEN-1):0] pc_rdata [(NHART-1):0][(RETIRE-1):0], // PC of insn
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output logic [(XLEN-1):0] pc_wdata [(NHART-1):0][(RETIRE-1):0], // PC of next instruction
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// X Registers
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output logic [31:0][(XLEN-1):0] x_wdata [(NHART-1):0][(RETIRE-1):0], // X data value
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output logic [31:0] x_wb [(NHART-1):0][(RETIRE-1):0], // X data writeback (change) flag
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// F Registers
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output logic [31:0][(FLEN-1):0] f_wdata [(NHART-1):0][(RETIRE-1):0], // F data value
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output logic [31:0] f_wb [(NHART-1):0][(RETIRE-1):0], // F data writeback (change) flag
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// V Registers
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output logic [31:0][(VLEN-1):0] v_wdata [(NHART-1):0][(RETIRE-1):0], // V data value
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output logic [31:0] v_wb [(NHART-1):0][(RETIRE-1):0], // V data writeback (change) flag
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// Control & State Registers
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output logic [4095:0][(XLEN-1):0] csr [(NHART-1):0][(RETIRE-1):0], // Full CSR Address range
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output logic [4095:0] csr_wb [(NHART-1):0][(RETIRE-1):0], // CSR writeback (change) flag
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output logic lrsc_cancel[(NHART-1):0][(RETIRE-1):0] // Implementation defined cancel
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);
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assign clk = dut.clk;
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// *** need to pipeline to writeback stage.
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assign valid = dut.core.ieu.InstrValidM;
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assign insn = dut.core.ifu.InstrM;
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assign pc_rdata = dut.core.ifu.PCM;
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always_ff @(posedge clk) begin
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if(valid) begin
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$display("PC = %d, insn = %d", pc_rdata, insn);
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end
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end
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//
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// Synchronization of NETs
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//
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wire clkD;
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assign #1 clkD = clk;
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string name[$];
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int value[$];
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longint tslot[$];
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int nets[string];
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function automatic void net_push(input string vname, input int vvalue);
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longint vslot = $time;
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name.push_front(vname);
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value.push_front(vvalue);
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tslot.push_front(vslot);
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endfunction
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function automatic int net_pop(output string vname, output int vvalue, output longint vslot);
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int ok;
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string msg;
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if (name.size() > 0) begin
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vname = name.pop_back();
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vvalue = value.pop_back();
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vslot = tslot.pop_back();
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nets[vname] = vvalue;
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ok = 1;
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end else begin
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ok = 0;
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end
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return ok;
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endfunction
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endmodule
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-----/\----- EXCLUDED -----/\----- */
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